Meet Patel 108db1bc12 test(ulp): snapshot LP ADC raw reads after GPIO settle ...

HP was asserting a live LP buffer and starting firmware before ADC/GPIO setup.
That produced leftover-high values and print/assert mismatches on pull-down.

Wait 100 ms for analog settle, then wait for completed scans with a wall-clock
timeout (pdMS_TO_TICKS(1) is zero at a 10 ms tick). Copy a local snapshot and
assert it; do not retry until a reading is in range. Deinit on teardown so a
failed raw-read cannot abort the following stress case.

2026-09-04 11:38:08 +05:30

..

lp_core

test(ulp): snapshot LP ADC raw reads after GPIO settle

2026-09-04 11:38:08 +05:30

ulp_fsm

test(ulp): added larger delay in ULP FSM I_WR_REG instruction test

2025-11-17 16:03:21 +08:00

ulp_riscv

fix(ci): reduce peripheral multi dev test timeout time

2026-08-19 15:30:55 +08:00

.build-test-rules.yml

Merge branch 'feat/support_esp32s31_xtal_fosc_force_pu' into 'master'

2026-08-10 15:37:00 +08:00