mirror of
https://github.com/espressif/esp-idf.git
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106 lines
4.2 KiB
C
106 lines
4.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdatomic.h>
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#include <sys/queue.h>
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#include "esp_dma_utils.h"
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#include "esp_private/gdma.h"
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#include "hal/dma_types.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_pm.h"
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct uhci_controller_t uhci_controller_t;
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#define CONFIG_UHCI_ISR_HANDLER_IN_IRAM (0) // Should be set to 1 only if UHCI_ISR_CACHE_SAFE is 1
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#define CONFIG_UHCI_ISR_CACHE_SAFE (0) // Don't forget enable GDMA_ISR_HANDLER_IN_IRAM
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#define CONFIG_UHCI_ENABLE_DEBUG_LOG (0)
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#define UHCI_ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
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#define UHCI_MAX(a, b) (((a)>(b))?(a):(b))
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#define UHCI_PM_LOCK_NAME_LEN_MAX 16
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#if CONFIG_UHCI_ISR_HANDLER_IN_IRAM
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#define UHCI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define UHCI_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
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#endif
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#if SOC_PERIPH_CLK_CTRL_SHARED
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#define UHCI_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define UHCI_CLOCK_SRC_ATOMIC()
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#endif
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#if !SOC_RCC_IS_INDEPENDENT
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#define UHCI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define UHCI_RCC_ATOMIC()
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#endif
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typedef dma_descriptor_align4_t uhci_dma_descriptor_t;
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typedef struct {
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void *buffer; // buffer for saving the received symbols
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size_t buffer_size; // size of the buffer, in bytes
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} uhci_transaction_desc_t;
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typedef enum {
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UHCI_TX_FSM_ENABLE_WAIT, /**< FSM is waiting to enable the UHCI system. */
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UHCI_TX_FSM_ENABLE, /**< FSM is enabling the UHCI system. */
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UHCI_TX_FSM_RUN_WAIT, /**< FSM is waiting to transition to the running state. */
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UHCI_TX_FSM_RUN, /**< FSM is in the running state, actively handling UHCI operations. */
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} uhci_tx_fsm_t;
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typedef enum {
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UHCI_TRANS_QUEUE_READY, /**< The transaction queue is ready to accept new transactions. */
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UHCI_TRANS_QUEUE_PROGRESS, /**< A transaction is currently in progress. */
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UHCI_TRANS_QUEUE_COMPLETE, /**< All transactions in the queue are completed. */
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UHCI_TRANS_QUEUE_MAX, /**< Placeholder for the maximum number of states (not a valid state). */
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} uhci_trans_queue_enum_t;
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typedef enum {
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UHCI_RX_FSM_ENABLE_WAIT, /**< FSM is waiting to enable the UHCI system. */
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UHCI_RX_FSM_ENABLE, /**< FSM is enabling the UHCI system. */
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UHCI_RX_FSM_RUN_WAIT, /**< FSM is waiting to transition to the running state. */
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UHCI_RX_FSM_RUN, /**< FSM is in the running state, actively handling UHCI operations. */
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} uhci_rx_fsm_t;
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typedef struct {
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gdma_channel_handle_t dma_chan; // GDMA channel
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uhci_tx_done_callback_t on_tx_trans_done; // tx transaction done callback function
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uhci_transaction_desc_t *trans_desc_pool; // transaction descriptor pool
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uhci_transaction_desc_t *cur_trans; // pointer to current transaction
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uhci_dma_descriptor_t *dma_nodes; // DMA descriptor nodes
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QueueHandle_t trans_queues[UHCI_TRANS_QUEUE_MAX]; // transaction queue
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_Atomic uhci_tx_fsm_t tx_fsm; // channel life cycle specific FSM
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size_t int_mem_align; // Alignment for internal memory
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size_t ext_mem_align; // Alignment for external memory
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atomic_int num_trans_inflight; // Indicates the number of transactions that are undergoing but not recycled to ready_queue
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} uhci_tx_dir;
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struct uhci_controller_t {
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int uhci_num; // UHCI port number
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uhci_hal_context_t hal; // uhci hal layer context
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uhci_tx_dir tx_dir; // tx direction structure
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void *user_data; // user data
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size_t int_mem_cache_line_size; // internal memory cache line size
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size_t ext_mem_cache_line_size; // external memory cache line size
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esp_pm_lock_handle_t pm_lock; // power management lock
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char pm_lock_name[UHCI_PM_LOCK_NAME_LEN_MAX]; // pm lock name
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};
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#ifdef __cplusplus
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}
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#endif
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