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224 lines
8.4 KiB
Plaintext
224 lines
8.4 KiB
Plaintext
menu "RISC-V Trace Encoder Configurations"
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depends on SOC_RISCV_TRACE_SUPPORTED
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config ESP_RISCV_TRACE_ENABLE
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bool "Enable ESP RISC-V trace encoder"
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default n
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help
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Build the ESP RISC-V trace encoder driver and expose its runtime API.
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if ESP_RISCV_TRACE_ENABLE
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config ESP_RISCV_TRACE_BUFFER_SIZE
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int "Trace buffer size (bytes)"
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default 2048
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help
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Size in bytes of the trace buffer allocated by the driver.
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choice ESP_RISCV_TRACE_BUFFER_MEM_SELECT
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prompt "Trace buffer memory placement"
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default ESP_RISCV_TRACE_BUFFER_IN_INTERNAL
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help
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Where the driver allocates the trace buffer. The encoder writes the buffer over
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its AHB master. PSRAM is only offered on targets whose encoder can reach it.
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Internal RAM is fastest and always usable. PSRAM frees internal RAM and allows
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much larger buffers, but is slower (higher risk of FIFO overflow at high trace
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rates) and is inaccessible while the cache is disabled (e.g. during flash writes).
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config ESP_RISCV_TRACE_BUFFER_IN_INTERNAL
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bool "Internal RAM"
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config ESP_RISCV_TRACE_BUFFER_IN_EXTERNAL
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bool "External RAM (PSRAM)"
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depends on SPIRAM && SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
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endchoice
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config ESP_RISCV_TRACE_BUFFER_MEM
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int
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default 0 if ESP_RISCV_TRACE_BUFFER_IN_INTERNAL
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default 1 if ESP_RISCV_TRACE_BUFFER_IN_EXTERNAL
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choice ESP_RISCV_TRACE_CORE_SELECT
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prompt "Cores to trace"
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default ESP_RISCV_TRACE_BOTH_CORES if SOC_HP_CPU_HAS_MULTIPLE_CORES && !FREERTOS_UNICORE
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default ESP_RISCV_TRACE_CORE_0
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help
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Select which RISC-V core(s) the trace encoder is set up for. Each traced core
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gets its own encoder instance and trace buffer, so tracing both cores doubles
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the memory used.
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config ESP_RISCV_TRACE_CORE_0
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bool "Core 0 only"
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config ESP_RISCV_TRACE_CORE_1
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bool "Core 1 only"
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depends on SOC_HP_CPU_HAS_MULTIPLE_CORES && !FREERTOS_UNICORE
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config ESP_RISCV_TRACE_BOTH_CORES
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bool "Both cores"
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depends on SOC_HP_CPU_HAS_MULTIPLE_CORES && !FREERTOS_UNICORE
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endchoice
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config ESP_RISCV_TRACE_CORE_MASK
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hex
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default 0x1 if ESP_RISCV_TRACE_CORE_0
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default 0x2 if ESP_RISCV_TRACE_CORE_1
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default 0x3 if ESP_RISCV_TRACE_BOTH_CORES
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choice ESP_RISCV_TRACE_ADDRESS_MODE_SELECT
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prompt "Instruction address encoding"
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depends on SOC_RISCV_TRACE_HAS_CONFIG_REG
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default ESP_RISCV_TRACE_ADDRESS_MODE_DELTA
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help
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How instruction addresses are encoded in the trace stream.
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config ESP_RISCV_TRACE_ADDRESS_MODE_DELTA
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bool "Delta addresses"
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config ESP_RISCV_TRACE_ADDRESS_MODE_FULL
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bool "Full addresses"
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endchoice
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config ESP_RISCV_TRACE_ADDRESS_MODE
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int
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default 0 if ESP_RISCV_TRACE_ADDRESS_MODE_DELTA
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default 1 if ESP_RISCV_TRACE_ADDRESS_MODE_FULL
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default 0
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choice ESP_RISCV_TRACE_MEM_MODE_SELECT
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prompt "Trace buffer memory mode"
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default ESP_RISCV_TRACE_MEM_MODE_LOOP
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help
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Behaviour of the trace buffer when it becomes full.
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config ESP_RISCV_TRACE_MEM_MODE_NON_LOOP
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bool "Stop when buffer is full"
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config ESP_RISCV_TRACE_MEM_MODE_LOOP
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bool "Wrap around (loop)"
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endchoice
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config ESP_RISCV_TRACE_MEM_MODE
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int
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default 0 if ESP_RISCV_TRACE_MEM_MODE_NON_LOOP
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default 1 if ESP_RISCV_TRACE_MEM_MODE_LOOP
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config ESP_RISCV_TRACE_AUTO_RESTART_ENABLE
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bool "Auto-restart encoder after a FIFO overflow"
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default n
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help
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A FIFO overflow stops the encoder. When enabled, it restarts automatically once
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the FIFO is empty again.
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config ESP_RISCV_TRACE_AUTO_RESTART
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int
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default 1 if ESP_RISCV_TRACE_AUTO_RESTART_ENABLE
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default 0
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config ESP_RISCV_TRACE_STALL_CPU_ENABLE
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bool "Stall CPU on FIFO full"
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depends on SOC_RISCV_TRACE_HAS_CONFIG_REG
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default n
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help
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Stall the CPU instead of dropping packets when the FIFO is full.
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config ESP_RISCV_TRACE_STALL_CPU
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int
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default 1 if ESP_RISCV_TRACE_STALL_CPU_ENABLE
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default 0
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config ESP_RISCV_TRACE_HALT_ENABLE
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bool "Report hart halt in the trace"
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depends on SOC_RISCV_TRACE_HAS_CONFIG_REG
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default n
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help
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When the hart halts, report the address of the last instruction before the halt;
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tracing resumes with a synchronization packet when the hart continues.
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config ESP_RISCV_TRACE_HALT
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int
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default 1 if ESP_RISCV_TRACE_HALT_ENABLE
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default 0
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config ESP_RISCV_TRACE_RESET_ENABLE
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bool "Report hart reset in the trace"
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depends on SOC_RISCV_TRACE_HAS_CONFIG_REG
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default n
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help
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When the hart enters reset, report the address of the last instruction before the
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reset. Tracing resumes with a synchronization packet afterwards.
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config ESP_RISCV_TRACE_RESET
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int
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default 1 if ESP_RISCV_TRACE_RESET_ENABLE
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default 0
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config ESP_RISCV_TRACE_DEBUG_TRIGGER_ENABLE
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bool "Enable Debug Module trigger input"
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depends on SOC_RISCV_TRACE_HAS_CONFIG_REG
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default n
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help
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Enable the Debug Module trigger input to the trace encoder.
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config ESP_RISCV_TRACE_DEBUG_TRIGGER
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int
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default 1 if ESP_RISCV_TRACE_DEBUG_TRIGGER_ENABLE
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default 0
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choice ESP_RISCV_TRACE_RESYNC_MODE_SELECT
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prompt "Resynchronization mode"
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default ESP_RISCV_TRACE_RESYNC_MODE_DISABLED
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help
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Periodic resynchronization mode of the trace encoder.
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config ESP_RISCV_TRACE_RESYNC_MODE_DISABLED
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bool "Disabled"
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config ESP_RISCV_TRACE_RESYNC_MODE_PACKET
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bool "By packet count"
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config ESP_RISCV_TRACE_RESYNC_MODE_CYCLE
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bool "By cycle count"
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endchoice
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config ESP_RISCV_TRACE_RESYNC_MODE
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int
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default 0 if ESP_RISCV_TRACE_RESYNC_MODE_DISABLED
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default 2 if ESP_RISCV_TRACE_RESYNC_MODE_PACKET
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default 3 if ESP_RISCV_TRACE_RESYNC_MODE_CYCLE
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config ESP_RISCV_TRACE_RESYNC_THRESHOLD
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int "Resync threshold" if !ESP_RISCV_TRACE_RESYNC_MODE_DISABLED
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default 128
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help
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Threshold (packet or cycle count) used by the selected resynchronization mode.
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choice ESP_RISCV_TRACE_AHB_BURST_SELECT
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prompt "AHB burst type"
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depends on SOC_RISCV_TRACE_AHB_CONFIGURABLE
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default ESP_RISCV_TRACE_AHB_BURST_SINGLE
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help
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AHB burst type used by the trace write master.
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config ESP_RISCV_TRACE_AHB_BURST_SINGLE
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bool "Single transfer"
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config ESP_RISCV_TRACE_AHB_BURST_INCR
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bool "Incrementing (undefined length)"
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config ESP_RISCV_TRACE_AHB_BURST_INCR4
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bool "4-beat incrementing"
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config ESP_RISCV_TRACE_AHB_BURST_INCR8
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bool "8-beat incrementing"
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endchoice
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config ESP_RISCV_TRACE_AHB_BURST
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int
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default 0 if ESP_RISCV_TRACE_AHB_BURST_SINGLE
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default 1 if ESP_RISCV_TRACE_AHB_BURST_INCR
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default 2 if ESP_RISCV_TRACE_AHB_BURST_INCR4
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default 4 if ESP_RISCV_TRACE_AHB_BURST_INCR8
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default 0
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config ESP_RISCV_TRACE_AHB_MAX_INCR
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int "Max INCR burst beats" if SOC_RISCV_TRACE_AHB_CONFIGURABLE
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default 0
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help
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Maximum number of beats for an undefined-length INCR burst.
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endif # ESP_RISCV_TRACE_ENABLE
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endmenu
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