Files
esp-idf/components/soc
igor.masar eba0a57f95 feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3 and ESP32-P4 to
expose the number of FSLS USB_WRAP PHYs available on each target. This
separates FSLS USB_WRAP support from OTG/UTMI support so that downstream
code can gate FSLS PHY handling independently.
2026-04-24 13:30:58 +02:00
..

soc

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware