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72aba0e0c9
avoid critical issues caused by manual cache writeback and conflicting writes. The issue exist on chips after esp32p4
19 lines
748 B
Plaintext
19 lines
748 B
Plaintext
[mapping:esp_rom]
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archive: libesp_rom.a
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entries:
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esp_rom_spiflash (noflash)
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if ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG = y:
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esp_rom_cache_esp32s2_esp32s3 (noflash)
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if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y:
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esp_rom_cache_writeback_esp32s3 (noflash)
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if HEAP_TLSF_USE_ROM_IMPL = y && (ESP_ROM_TLSF_CHECK_PATCH = y || HEAP_TLSF_CHECK_PATCH = y):
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esp_rom_tlsf (noflash)
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if SOC_SYSTIMER_SUPPORTED = y:
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esp_rom_systimer (noflash)
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if HAL_WDT_USE_ROM_IMPL = y:
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esp_rom_wdt (noflash)
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if ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_MAP = y:
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esp_rom_cache_writeback_esp32p4 (noflash)
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if ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP = y:
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esp_rom_cache_writeback_esp32c61 (noflash)
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