Jiang Jiang Jian 94ace905b9 Merge branch 'feature/update_gdbstub_v6.0' into 'release/v6.0' ...

gdbstub: backport fixes (v6.0)

See merge request espressif/esp-idf!46200

2026-03-24 10:28:23 +08:00

..

baremetal

xtensa: Add bare metal port stub functions for G0 build test

2023-04-18 15:51:38 +08:00

deprecated_include

change(xtensa): Deprecate ".../xtensa_timer.h" include path

2023-11-30 21:58:52 +08:00

esp32

fix(gdbstub): xtensa: fix FPU registers read and write

2026-03-12 17:24:26 +07:00

esp32s2

refactor(xtensa): Rename specreg.h register macros

2025-06-17 15:37:33 +02:00

esp32s3

fix(gdbstub): xtensa: fix FPU registers read and write

2026-03-12 17:24:26 +07:00

include

fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop

2026-03-20 16:43:58 +08:00

trax

feat: Update esptool to v5

2025-09-30 15:28:55 +02:00

CMakeLists.txt

change(xtensa): use add_prebuilt_library to add blobs

2025-07-17 09:33:21 +08:00

eri.c

feat(license): Dual-license source files built by OpenOCD stub flasher

2024-01-15 23:45:23 +01:00

linker.lf

xtensa: Move Xtensa RTOS porting layer files to xtensa component

2023-04-18 15:28:05 +08:00

project_include.cmake

fix(xtensa/cmake): do not include project_include.cmake if the architecture is not xtensa

2025-11-04 07:48:13 +01:00

xt_trax.c

…

xtensa_context.S

refactor(xtensa): Rename specreg.h register macros

2025-06-17 15:37:33 +02:00

xtensa_intr_asm.S

refactor(xtensa): Rename specreg.h register macros

2025-06-17 15:37:33 +02:00

xtensa_intr.c

change(app_trace): move sysview to component registry

2025-11-13 10:50:42 +01:00

xtensa_loadstore_handler.S

fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop

2026-03-20 16:43:58 +08:00

xtensa_vectors.S

fix(esp32): Fix access to MALLOC_CAP_IRAM_8BIT byte array in loop

2026-03-20 16:43:58 +08:00