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22cc8d41c8
Declare ext_ram_xip_seg as a distinct region overlapping drom_seg at the same origin (the esp32s3/c5/c61/h4 pattern) instead of aliasing drom_seg, so .ext_ram.dummy has its own location counter and .ext_ram.bss reclaims the VMA space of NOLOAD rodata (.rodata_wlog_*), saving up to one MMU page of PSRAM on esp32s31. No layout change on esp32p4. Closes https://github.com/espressif/esp-idf/issues/18791 Related https://github.com/espressif/esp-idf/issues/14992
137 lines
4.9 KiB
Plaintext
137 lines
4.9 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* ESP32-S31 Linker Script Memory Layout
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* This file describes the memory layout (memory blocks) by virtual memory addresses.
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* This linker script is passed through the C preprocessor to include configuration options.
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* Please use preprocessor features sparingly!
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* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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#include "ld.common"
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#include "ld.hp_mem_defs"
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#define SRAM_START 0x2F000000
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#if CONFIG_ULP_COPROC_RUN_FROM_HP_MEM
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#define SRAM_SIZE (ULP_HP_MEM_START - SRAM_START)
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#else
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#define SRAM_SIZE (SRAM_SEG_END - SRAM_START)
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#endif
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#define IDROM_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 10)
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MEMORY
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{
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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/* PSRAM mapped instruction data */
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irom_seg (RX) : org = 0x50000020, len = IDROM_SEG_SIZE - 0x20
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#else
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/* Flash mapped instruction data */
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irom_seg (RX) : org = 0x40000020, len = IDROM_SEG_SIZE - 0x20
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/**
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* (0x20 offset above is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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#endif // CONFIG_SPIRAM_FETCH_INSTRUCTIONS
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
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*/
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sram_seg (RWX) : org = SRAM_START, len = SRAM_SIZE
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_RODATA
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/* PSRAM mapped constant data */
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drom_seg (R) : org = 0x50000020, len = IDROM_SEG_SIZE - 0x20
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#else
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/* Flash mapped constant data */
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drom_seg (R) : org = 0x40000020, len = IDROM_SEG_SIZE - 0x20
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#endif // CONFIG_SPIRAM_RODATA
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/* (See irom_seg for meaning of 0x20 offset in the above.) */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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* lp ram memory (RWX). Persists over deep sleep.
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*/
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#if CONFIG_ULP_COPROC_ENABLED
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lp_ram_seg(RW) : org = 0x2E000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x8000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
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#else
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lp_ram_seg(RW) : org = 0x2E000000, len = 0x8000 - RESERVE_RTC_MEM
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#endif // CONFIG_ULP_COPROC_ENABLED
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/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
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It reserves the amount of LP memory that we use for this memory segment.
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This segment is intended for keeping:
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- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
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The aim of this is to keep data that will not be moved around and have a fixed address.
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*/
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lp_reserved_seg(RW) : org = 0x2E000000 + 0x8000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
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/* PSRAM seg */
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extern_ram_seg(RWX) : org = 0x50000000, len = IDROM_SEG_SIZE
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#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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/**
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* Distinct region overlapping `drom_seg` at the same origin, so `.ext_ram.dummy`
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* gets its own location counter and `.ext_ram.bss` can reclaim the space of
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* NOLOAD rodata (e.g. `.rodata_wlog_*`).
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*/
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ext_ram_xip_seg(RWX) : org = 0x50000020, len = IDROM_SEG_SIZE - 0x20
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#endif // CONFIG_SPIRAM_XIP_FROM_PSRAM
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}
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000;
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REGION_ALIAS("iram_text_seg", sram_seg);
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REGION_ALIAS("dram_seg", sram_seg);
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/**
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* The lines below define location alias for .rtc.data section
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* S31 has no distinguished LP(RTC) fast and slow memory sections, instead, there is a unified LP_RAM section
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* Thus, the following region segments are not configurable like on other targets
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*/
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REGION_ALIAS("rtc_text_seg", lp_ram_seg);
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REGION_ALIAS("rtc_data_seg", lp_ram_seg);
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REGION_ALIAS("rtc_slow_seg", lp_ram_seg);
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REGION_ALIAS("rtc_force_fast_seg", lp_ram_seg);
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REGION_ALIAS("rtc_force_slow_seg", lp_ram_seg);
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REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg);
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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REGION_ALIAS("flash_text_seg", irom_seg);
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REGION_ALIAS("flash_rodata_seg", drom_seg);
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#else
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REGION_ALIAS("flash_text_seg", sram_seg);
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REGION_ALIAS("flash_rodata_seg", sram_seg);
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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REGION_ALIAS("ext_ram_seg", ext_ram_xip_seg);
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#else
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REGION_ALIAS("ext_ram_seg", extern_ram_seg);
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#endif //#if CONFIG_SPIRAM_XIP_FROM_PSRAM
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ALIGN_VECTOR_TABLE = 0x40;
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#if CONFIG_ULP_COPROC_RUN_FROM_HP_MEM
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_ulp_hp_mem_resv_start = ULP_HP_MEM_START;
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_ulp_hp_mem_resv_end = ULP_HP_MEM_END;
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#endif
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