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48 lines
3.2 KiB
ReStructuredText
48 lines
3.2 KiB
ReStructuredText
Cache Access Counters
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=====================
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:link_to_translation:`zh_CN:[中文]`
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Introduction
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------------
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{IDF_TARGET_NAME} has hardware counters attached to the cache request buses. They record the number of completed cache accesses, miss stall events, requester conflicts, and cache lines transferred to and from the next level of the memory hierarchy. These counters can be used to measure the cache hit/miss behavior of a piece of code, for example to choose the placement of data in memory, or to find out why some code runs slower than expected.
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Counter Units
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-------------
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The set of counters differs between chips: the number of cache levels, the number of request buses per cache, and which counters exist per bus all vary. Instead of a fixed list of caches, the API exposes a chip-defined list of counter *units*. Each unit is one set of counters observing one traffic stream, for example instruction fetches from core 0 into the L1 cache. Applications enumerate the units at runtime using :cpp:func:`esp_cache_cnt_num_units` and :cpp:func:`esp_cache_cnt_get_unit_info`, so they keep working when a new chip adds or removes units.
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Usage
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-----
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1. Call :cpp:func:`esp_cache_cnt_start` to clear and enable all counters.
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2. Run the code to be measured.
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3. Call :cpp:func:`esp_cache_cnt_stop` to disable the counters, so that reading out and reporting the results is not counted as well.
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4. Call :cpp:func:`esp_cache_cnt_dump` to print a table of all counter values, or read the values of individual units with :cpp:func:`esp_cache_cnt_get`.
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:cpp:func:`esp_cache_cnt_clear` resets the counters without changing whether they are running, which is useful when the counters have to stay enabled across measurement phases.
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Counter Semantics
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-----------------
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For each unit, :cpp:func:`esp_cache_cnt_get` returns:
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- ``accesses``: the number of completed accesses. The hardware "hit" counter increments once for every access that completes, whether or not the access had to wait for a line fill first, so it is reported as the total access count.
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- ``stall_events``: incremented repeatedly while an access is stalled on a miss. This value grows with the total miss latency, not with the number of missed accesses, so it is only useful as a relative measure.
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- ``conflicts``: the number of conflicts between requesters on the cache.
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- ``line_fills``: the number of lines fetched from the next level of the memory hierarchy. This is the true miss count.
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- ``writebacks``: the number of lines written back to the next level. Only present for data traffic on chips with a write-back cache.
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The miss ratio of a unit is therefore ``line_fills / accesses``, available as :cpp:func:`esp_cache_cnt_miss_ratio`. Not every counter exists for every unit; a field of :cpp:struct:`esp_cache_cnt_data_t` is only meaningful if the corresponding bit of the ``valid_mask`` member is set.
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Application Examples
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--------------------
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- :example:`system/cache_counters` runs a read workload over working sets of different sizes and placements, and prints the counter values after each run, showing how the working set size determines which level of the memory hierarchy serves the accesses.
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API Reference
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-------------
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.. include-build-file:: inc/esp_cache_cnt.inc
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