Alexey Lapshin 61a7342acd tools: add riscv zicsr/zifencei because they were separated from i ...

https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/aE1ZeHHCYf4

2023-02-22 05:33:03 +00:00

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cmake

tools: add riscv zicsr/zifencei because they were separated from i

2023-02-22 05:33:03 +00:00

ld

ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3

2022-09-05 10:21:43 +02:00

test_apps

TWDT: Use the new TWDT Kconfig options in the examples and tests

2023-02-17 11:22:25 +08:00

ulp_common

ulp-fsm: Update ulp-fsm ADC example with S3 support

2022-09-07 16:48:06 +08:00

ulp_fsm

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ulp_riscv

ulp-riscv: Added API ulp_riscv_reset to reset the ULP core

2023-02-08 07:52:34 +00:00

.build-test-rules.yml

ci: Modify build-test-rules.yml enable' to disable` to exclude preview targets

2022-09-01 12:38:00 +08:00

CMakeLists.txt

ulp-fsm: Update ulp-fsm ADC example with S3 support

2022-09-07 16:48:06 +08:00

component_ulp_common.cmake

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esp32ulp_mapgen.py

ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup

2022-08-30 02:34:28 +02:00

Kconfig

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project_include.cmake

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sdkconfig.rename.esp32

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sdkconfig.rename.esp32s2

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