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23 lines
945 B
Plaintext
23 lines
945 B
Plaintext
/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ESP32-P4 target-specific HP memory definitions shared between HP app and LP Core linker scripts */
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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#define SRAM_MAIN_END 0x4FF2CBD0 /* 2nd stage bootloader iram_loader_seg start address (rev < 3) */
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#else
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#define SRAM_MAIN_END 0x4FFAEFC0 /* 2nd stage bootloader iram_loader_seg start address (rev3+) */
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#endif
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#if CONFIG_ULP_COPROC_RUN_FROM_HP_MEM
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#define ULP_HP_MEM_SIZE CONFIG_ULP_COPROC_RESERVE_HP_MEM_BYTES
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/* Align down to 64-byte cache line boundary */
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#define ULP_HP_MEM_START ((SRAM_MAIN_END - ULP_HP_MEM_SIZE) & ~(64 - 1))
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/* Align down to 64-byte cache line boundary so that ULP_HP_MEM_END - ULP_HP_MEM_START
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* is always a multiple of the cache line size, satisfying esp_cache_msync alignment */
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#define ULP_HP_MEM_END (SRAM_MAIN_END & ~(64 - 1))
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#endif
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