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0ce211539a
On RISC-V chips with SPIRAM support (esp32c5, esp32c61, esp32h4, esp32p4, esp32s31), esp_restart_noos() was disabling the cache while the current stack pointer could still be in external RAM. Any stack access after cache disable (function call, local variable spill) would then fault with "Cache disabled but cached memory region accessed". Xtensa chips (esp32, esp32s2, esp32s3) already had this guard via the SET_STACK macro. Add the equivalent for RISC-V: - Add rv_utils_set_sp() to riscv/rv_utils.h (plain "mv sp, %0" with a memory clobber; no window register management needed on RISC-V) - In each affected system_internal.c, under CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM, check whether the current SP is in PSRAM and if so switch it to the top of internal BSS before any cache disable or writeback operation - Fix xTaskCreateStaticPinnedToCore() stack size argument in the spiram_stack test (was passing bytes instead of word count) - Mark the null-pointer write in func_do_exception() as volatile to prevent the compiler from optimizing it away - Extend the [spiram_stack] tests to RISC-V by sharing fibonacci() and the task/finish helpers across architectures, guarding only the Xtensa-specific WINDOWBASE/WINDOWSTART prints