mirror of
https://github.com/espressif/esp-idf.git
synced 2026-09-22 13:01:16 +03:00
0580cff0e4
Both PSRAM layouts were mapped as a single RWX window, so everything in external RAM - the heap included - was executable. PSRAM used as data only is now RW, and under XIP-from-PSRAM it is split per section as ESP32-P4 does: .text RX, .rodata read-only, and the MMU-page alignment gaps and the reclaimed heap RW, so neither is executable. Both describe the layout that esp_psram_init() produces, and the entries are locked, so - again as on ESP32-P4 - they are only narrowed when CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION says that layout applies. Without it the application owns the region and PSRAM stays RWX. The per-section entries cost one PMP entry more than the 16 available, so the CPU subsystem and peripheral windows are chained as TOR entries, taking one entry instead of three. soc.h is corrected against the S31 bus address map: the peripheral window base was 1 MB too low, and the LP peripheral top, derived from a register base plus a size rather than from the map, was 16 KB short. SOC_NON_CACHEABLE_OFFSET_FLASH is added.