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da41d31a14
ECDSA enable pulses a reset that also holds SHA in reset, and SHA shares its DMA with AES. Key Manager enable pulses a reset that also covers the XTS-AES flash encryption key-usage selector. Neither path was serialized against those victims, so a hardware ECDSA/HMAC/DS operation could corrupt a concurrent SHA/AES transfer or an in-flight encrypted flash read. - Take the SHA/AES lock inside esp_crypto_ecdsa_lock_acquire(), before MPI, matching the DS lock order (sha_aes < mpi) - Add esp_crypto_key_mgr_enable_periph_clk_no_reset() and switch ECDSA, HMAC and DS to it; they only need the key-usage selector writable - Hold esp_crypto_key_manager_lock across those clock enable/disable pairs so selector writes stay serialized without resetting KM