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morrisandCursor
2972e03b3f
PSRAM DQS delayline tuning calls mspi_timing_config_psram_set_tuning_delayline() once per sample (~3100 times on ESP32-P4). A DEBUG print there blocks on UART long enough to trip the bootloader RTC WDT (default 9s), so DEBUG builds reset-loop and never reach app_main(). Remove that per-sample log. The selected phase is already reported once by the phase-tuning stage. Add a startup test config that boots with SPIRAM and DEBUG logging. Closes https://github.com/espressif/esp-idf/issues/19158 Co-authored-by: Cursor <cursoragent@cursor.com>
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
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