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https://github.com/espressif/esp-idf.git
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edbf8856ae
Add internal EMAC support for ESP32-S31, including: - HAL/LL layer: emac_ll, emac_hal, emac_clk, emac_periph for S31 - SOC layer: register structs, soc_caps, peripherals linker script, interrupt definitions - MAC driver: clock source configuration via Kconfig, GPIO/DMA adaptations, PHY register defs for clause-45 MDIO - Ethernet examples updated for S31 (basic, build-test-rules, PTP readme) - Refactored existing ESP32/ESP32-P4 EMAC code for shared patterns (emac_clk extraction, struct alignment, periph descriptor cleanup)
182 lines
7.2 KiB
Plaintext
182 lines
7.2 KiB
Plaintext
menu "Ethernet"
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# Invisible item that is enabled if any Ethernet selection is made
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config ETH_ENABLED
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bool
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menuconfig ETH_USE_ESP32_EMAC
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depends on SOC_EMAC_SUPPORTED
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bool "Support ESP32 internal EMAC controller"
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default y
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select ETH_ENABLED
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help
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ESP32 integrates a 10/100M Ethernet MAC controller.
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if ETH_USE_ESP32_EMAC
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config ETH_DMA_BUFFER_SIZE
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int "Ethernet DMA buffer size (Byte)"
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range 256 1600
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default 512
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help
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Set the size of each buffer used by Ethernet MAC DMA.
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!! Important !! Make sure it is 64B aligned for ESP32P4/S31!
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config ETH_DMA_RX_BUFFER_NUM
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int "Amount of Ethernet DMA Rx buffers"
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range 3 30
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default 10 if IDF_TARGET_ESP32 #ESP32 has bigger internal Rx FIFO
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default 20
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help
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Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
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Larger number of buffers could increase throughput somehow.
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config ETH_DMA_TX_BUFFER_NUM
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int "Amount of Ethernet DMA Tx buffers"
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range 3 30
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default 10
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help
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Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
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Larger number of buffers could increase throughput somehow.
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if ETH_DMA_RX_BUFFER_NUM > 15
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config ETH_SOFT_FLOW_CONTROL
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bool "Enable software flow control"
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default n
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help
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Ethernet MAC engine on ESP32 doesn't feature a flow control logic.
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The MAC driver can perform a software flow control if you enable this option.
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Note that, if the RX buffer number is small, enabling software flow control will
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cause obvious performance loss.
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endif
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config ETH_IRAM_OPTIMIZATION
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bool "Enable IRAM optimization"
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default n
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help
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If enabled, functions related to RX/TX are placed into IRAM. It can improve Ethernet throughput.
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If disabled, all functions are placed into FLASH.
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menu "Ethernet Time"
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depends on SOC_EMAC_IEEE1588V2_SUPPORTED
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config ETH_CLOCK_ADJTIME_PERIOD_MS
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int "Period over which adjtime() applies corrections (ms)"
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default 1000
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range 100 10000
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help
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The time period over which a clock_adjtime() correction is applied
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by adjusting the hardware clock rate. The PTP clock's tick rate (ppb)
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is computed as: ppb = delta_ns * 1000 / ETH_CLOCK_ADJTIME_PERIOD_MS.
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config ETH_CLOCK_ADJTIME_SLEWLIMIT_PPB
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int "Maximum clock slew rate (ppb)"
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default 500000
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range 1000 5000000
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help
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Drift estimates exceeding this limit (in ppb) are rejected as
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out of range. Typical crystal oscillators drift less than 50 ppm
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(50000 ppb).
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endmenu
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menu "Ethernet Clock"
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choice ETH_EMAC_PHY_REF_CLK_SRC
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prompt "PHY reference clock source"
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depends on !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
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default ETH_EMAC_PHY_REF_CLK_SRC_AUTO
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help
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Select the PLL clock source used to drive the PHY reference clock output
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(PLL_F50M). This applies to two scenarios: RMII mode with EMAC_CLK_OUT when
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the output clock is looped back externally, and RGMII mode when an optional
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50 MHz PHY_REF_CLK output is enabled (clock_phy_ref_gpio != -1).
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config ETH_EMAC_PHY_REF_CLK_SRC_AUTO
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bool "Auto"
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help
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Let the driver select the clock source automatically based on the
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hardware abstraction layer defaults.
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config ETH_EMAC_PHY_REF_CLK_SRC_MPLL
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bool "MPLL"
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depends on IDF_TARGET_ESP32S31
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help
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Use MPLL as the PHY reference clock source.
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config ETH_EMAC_PHY_REF_CLK_SRC_CPLL
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bool "CPLL"
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depends on IDF_TARGET_ESP32S31
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help
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Use CPLL as the PHY reference clock source.
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endchoice
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choice ETH_EMAC_RGMII_TX_CLK_SRC
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prompt "RGMII Tx clock source"
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depends on SOC_EMAC_SUPPORT_1000M
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default ETH_EMAC_RGMII_TX_CLK_SRC_AUTO
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help
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Select the PLL clock source used to generate the EMAC RGMII Tx clock output.
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config ETH_EMAC_RGMII_TX_CLK_SRC_AUTO
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bool "Auto"
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help
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Let the driver select the clock source automatically based on the
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hardware abstraction layer defaults.
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config ETH_EMAC_RGMII_TX_CLK_SRC_MPLL
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bool "MPLL"
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depends on IDF_TARGET_ESP32S31
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help
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Use MPLL as the RGMII Tx clock source.
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config ETH_EMAC_RGMII_TX_CLK_SRC_CPLL
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bool "CPLL"
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depends on IDF_TARGET_ESP32S31
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help
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Use CPLL as the RGMII Tx clock source.
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config ETH_EMAC_RGMII_TX_CLK_SRC_APLL
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bool "APLL"
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depends on IDF_TARGET_ESP32S31
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help
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Use Audio PLL (APLL) as the RGMII Tx clock source.
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endchoice
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endmenu
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endif # ETH_USE_ESP32_EMAC
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menuconfig ETH_USE_SPI_ETHERNET
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bool "Support SPI to Ethernet Module"
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default y
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select ETH_ENABLED
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help
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ESP-IDF can also support SPI-Ethernet. Actual chip drivers are available as components in
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Component Registry.
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menuconfig ETH_USE_OPENETH
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bool "Support OpenCores Ethernet MAC (for use with QEMU)"
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default n
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select ETH_ENABLED
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help
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OpenCores Ethernet MAC driver can be used when an ESP-IDF application
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is executed in QEMU. This driver is not supported when running on a
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real chip.
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if ETH_USE_OPENETH
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config ETH_OPENETH_DMA_RX_BUFFER_NUM
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int "Number of Ethernet DMA Rx buffers"
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range 1 64
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default 4
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help
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Number of DMA receive buffers, each buffer is 1600 bytes.
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config ETH_OPENETH_DMA_TX_BUFFER_NUM
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int "Number of Ethernet DMA Tx buffers"
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range 1 64
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default 1
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help
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Number of DMA transmit buffers, each buffer is 1600 bytes.
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endif # ETH_USE_OPENETH
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config ETH_TRANSMIT_MUTEX
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depends on ETH_ENABLED
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bool "Enable Transmit Mutex"
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default n
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help
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Prevents multiple accesses when Ethernet interface is used as shared resource and multiple
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functionalities might try to access it at a time.
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endmenu
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