morris
74d9e99d91
refactor(lcdcam): move shared core clock setup to drivers
...
Configure the shared LCDCAM core clock through guarded LCD and CAM LL APIs,
and unify LCD functional clock LL calls around group IDs across supported targets.
Co-authored-by: Cursor <cursoragent@cursor.com >
2026-07-27 18:40:04 +08:00
wuzhenghui
11ccd4c304
feat(esp_hw_support): support esp32s31 clock tree management
2026-07-22 16:32:12 +08:00
hebinglin
7d6c54996a
feat(esp_hw_support): support esp32h4 esp32s31 bus hw low power
2026-07-14 18:14:07 +08:00
wuzhenghui
ba1df35672
fix(esp_hw_support): fix esp32s31 mpll initialization
2026-06-25 12:20:57 +08:00
wuzhenghui
9d824a9c33
feat(esp_system): support esp32s31 esp_perip_clk_init
2026-06-10 21:20:03 +08:00
Ondrej Kosta
c7d6c41198
feat(clk_tree): support derived PLL clocks
...
Add a generic derived-PLL clock engine to esp_clk_tree_common that
handles acquire/release, mux selection, and divider programming for
target-defined derived clocks. Per-target descriptors (ESP32-P4,
ESP32-S31) plug into the engine via
esp_clk_tree_get_derived_clk_desc().
2026-05-21 15:59:42 +08:00
armando
f408e1a8bc
feat(sdmmc): add esp32s31 support
...
Enable SDMMC host support on ESP32-S31 across HAL, SOC caps, tests, examples, and documentation.
2026-05-21 09:09:28 +08:00
gaoxu
4e3751b32e
feat(cam): support dvp cam on ESP32-S31
2026-05-14 17:09:49 +08:00
wuzhenghui
3f6957450f
feat(esp_hw_support): support psram PD_TOP retention
2026-05-07 12:02:01 +08:00
wuzhenghui
f1f3f204fe
feat(esp_hw_support): support esp32s31 lightsleep/deepsleep example
2026-05-06 20:15:01 +08:00
hongshuqing
7c665c106c
fix(pmu): update cpll_bbpll_apll_mpll enable config
2026-04-27 14:30:19 +08:00
laokaiyao
8d0fca08a0
feat(i2s): support i2s & apll on esp32s31
2026-04-22 09:30:53 +08:00
Chen Ji Chang
83e7b11716
Merge branch 'feat/lcd_use_apll_clock' into 'master'
...
refactor(clk_tree): use general api to enable the clk
Closes IDF-11478 and IDF-12972
See merge request espressif/esp-idf!35952
2026-04-20 22:12:01 +08:00
Xorlent
51d059232b
Fix output bit range in bitscrambler documentation
...
Destination bit range incorrect in `Sub-instructions` example
2026-04-17 17:20:28 +08:00
Chen Jichang
6e206dd173
refactor(clk_tree): use general api to enable the clk
2026-04-16 20:03:06 +08:00
wuzhenghui
b913f147ba
feat(esp_hw_support): support esp32s31 esp_clock_output
2026-04-14 12:19:07 +08:00
Song Ruo Jing
50051b74a5
feat(clk): support for esp32s31 clock tree
2026-04-02 20:39:59 +08:00
armando
ebbd9cdb59
feat(psram): support psram device driver
2026-03-31 13:56:43 +08:00
Song Ruo Jing
600bf5b6d7
refactor(esp_hal_regi2c): move regi2c implementation from esp_rom to esp_hal_regi2c
2026-03-10 15:08:51 +08:00
Song Ruo Jing
62511d61e9
refactor(clk): split clock HAL into separate component
2026-01-13 15:50:20 +08:00
