Move print_memprot_err_details() and its state out of the RISC-V panic_arch.c
into port/panic_memprot.c behind panic_memprot_fill_info(), so the report can
be shared with the Xtensa PMS targets. No functional change.
Let panic-related components register their hooks through
esp_sys_event so panic sequencing stays extensible without
hardcoded esp_system dependencies.
On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.
Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.
Erhan Kurubas
harshal.patil
Marius Vikhammer
gaoxiaojie
wuzhenghui
Jakob Hasse
Renz Bagaporo
Alexey Gerenkov