Commit Graph
21 Commits
Author SHA1 Message Date
Jiang Jiang Jian cc5a3fbcb5 Merge branch 'feat/psram_enc_exempt_v5.5' into 'release/v5.5'
feat(esp_psram): add option to carve unencrypted PSRAM region (v5.5)

See merge request espressif/esp-idf!49931
2026-07-16 17:04:28 +08:00
wuzhenghui 1b3d83528b change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT caps 2026-07-09 17:33:25 +08:00
Mahavir Jain 6d51abfc4c docs(esp_psram): clarify carve-out location is at upper end of PSRAM
The previous wording "top of PSRAM" was ambiguous: the carve-out is
actually mapped at the highest physical addresses of PSRAM (after the
rodata, text, and main heap mappings). Update the Kconfig help text for
SPIRAM_ENC_EXEMPT and SPIRAM_ENC_EXEMPT_SIZE, the External RAM
documentation, and the internal layout comment to say "upper end of PSRAM
(highest physical addresses)" instead.
2026-06-23 14:56:41 +05:30
Mahavir Jain afdf1a5259 feat(esp_psram): add esp_psram_ptr_is_no_enc() helper
Drivers that allocate from the unencrypted PSRAM carve-out via
MALLOC_CAP_SPIRAM_NO_ENC currently have no way to verify after the fact
which pool a buffer came from. This is particularly relevant for callers
using heap_caps_malloc_prefer(MALLOC_CAP_SPIRAM_NO_ENC, MALLOC_CAP_SPIRAM),
where a silent fallback to encrypted PSRAM would still pass the typical
esp_ptr_external_ram() check.

Expose esp_psram_ptr_is_no_enc() in the public esp_psram.h header. It
performs a range check against the carve-out's virtual-address window and
returns false when PSRAM is not initialized or CONFIG_SPIRAM_ENC_EXEMPT is
disabled, so callers do not need to guard the call site with #if.

Also reference the helper from the External RAM documentation alongside
the heap_caps_malloc(MALLOC_CAP_SPIRAM_NO_ENC) usage example.
2026-06-23 14:56:40 +05:30
Mahavir Jain 656a5857eb fix(esp_psram): handle carve-out vaddr exhaustion and add region to self-test
If the virtual-address pool is exhausted when reserving the unencrypted
PSRAM carve-out (the warning at L388 may already have fired for the main
mapping), esp_mmu_map_reserve_block_with_caps() returns an error rather
than aborting. Convert the previous assert() into a logged fallback that
disables the carve-out for this boot, mirroring the SPIRAM_ENC_EXEMPT_SIZE
>= psram_available_size path.

Also extend esp_psram_extram_test() to run the standard memory test on
the carve-out region when CONFIG_SPIRAM_ENC_EXEMPT is enabled, so the
unencrypted mapping is exercised on startup like the other PSRAM regions.
2026-06-23 14:56:40 +05:30
harshal.patil 1fde0259fe change(esp_psram): Consider all PSRAM regions in PMP protection 2026-06-23 14:56:39 +05:30
Mahavir Jain 0044542811 feat(esp_psram): add option to carve unencrypted PSRAM region
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
2026-06-23 14:56:38 +05:30
Xiao Xufeng bb79e6f246 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-19 17:53:51 +08:00
morris 9e1c0fc4ee Merge branch 'fix/psram_encryption_warning_c5c61_v5.5' into 'release/v5.5'
fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on... (v5.5)

See merge request espressif/esp-idf!44622
2026-01-16 09:58:25 +08:00
armando 67a1e80e51 fix(mspi): fixed mspi dma burst timing issue 2026-01-15 14:11:05 +08:00
Xiao Xufeng a4aff97a21 fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on ESP32-C5 v1.2 and C61 v1.1 2026-01-13 18:00:18 +08:00
armando 7b9f5b85a7 fix(psram): fixed p4 rev3 xip stuck after board reset issue 2025-10-23 17:00:24 +08:00
Mahavir Jain 2829481eb6 fix(psram): provide boot warning about PSRAM encryption issue on C5/C61
For C5/C61 revision 1.0, PSRAM encryption has hardware issue. This will
be addressed in future silicon version. Add explicit warning about this.
2025-08-11 13:46:38 +05:30
armando 30d77f494e fix(psram): fixed psram ptr check under xip_psram condition
Closes https://github.com/espressif/esp-idf/pull/15999
Closes https://github.com/espressif/esp-idf/issues/15997
2025-06-11 06:44:21 +00:00
John Boiles 7557ec0951 fix(memory-utils): Add _instruction_reserved_start/end to esp_psram_check_ptr_addr
Adds missing range check that can be used when SPIRAM_XIP_FROM_PSRAM is enabled.
2025-06-11 06:44:21 +00:00
harshal.patil 3123fff18a fix(esp_psram): Add XIP PSRAM alignment gaps in heap only if PSRAM protection is enabled 2025-05-05 10:50:19 +05:30
harshal.patil ab229a34b3 feat(cpu_region_protect): Enable basic memory protection for SPIRAM 2025-04-29 11:48:27 +05:30
harshal.patil 49f253361e feat(esp_psram): Add the gap created due to alignment of XIP segments in heap 2025-04-29 11:48:27 +05:30
harshal.patil 0f628496c8 feat(esp_psram): Add some helper APIs to get usable PSRAM memory size 2025-04-29 11:48:27 +05:30
harshal.patil 46225a4026 feat(esp_psram): Add a new API to just detect and enable the PSRAM
- esp_psram_chip_init() just detects and does basic initialisations of PSRAM
- esp_psram_init() initialises and maps/loads the PSRAM pages
2025-04-29 11:48:27 +05:30
armando ac8cfadab0 refactor(psram): cleanup psram component code structure 2025-03-20 15:17:01 +08:00