Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21 and esp32p4. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
Guard external-cache suspend for pure-ram apps where esp_cache_utils is
not linked, and move esp32p4-only xip_psram sdkconfig options into a
target-specific file to avoid unknown-kconfig failures on other chips.
The digest length and the condition that reserves it at the end of RTC RAM were
duplicated in seven places. Hold the reservation in a hidden Kconfig value that
is zero when the feature does not apply, so every consumer subtracts it
unconditionally, and derive ESP_SECURE_BOOT_DIGEST_LEN from it.
Default timeout for interrupt WDT was increased by default
on ESP32, due to some heap integrity check APIs taking a long
time on large PSRAMs and causing timeouts.
But this adjustment was only done for ESP32, not later chips,
even though they may experience the same issue.
Adjusted to have the same behavior on all chips with PSRAM
enabled, making it consistant with the docs.
Closes https://github.com/espressif/esp-idf/issues/18360
This is a workaround for rom code issue, which can cause the chip to end in infinite loop
when reset is triggered from esptool/idf-monitor. This is only applicable to ESP32-C5 rev <= 1.0.
Closes https://github.com/espressif/esp-idf/issues/18089
On RISC-V chips with SPIRAM support (esp32c5, esp32c61, esp32h4, esp32p4,
esp32s31), esp_restart_noos() was disabling the cache while the current
stack pointer could still be in external RAM. Any stack access after cache
disable (function call, local variable spill) would then fault with
"Cache disabled but cached memory region accessed".
Xtensa chips (esp32, esp32s2, esp32s3) already had this guard via the
SET_STACK macro. Add the equivalent for RISC-V:
- Add rv_utils_set_sp() to riscv/rv_utils.h (plain "mv sp, %0" with a
memory clobber; no window register management needed on RISC-V)
- In each affected system_internal.c, under
CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM, check whether the current
SP is in PSRAM and if so switch it to the top of internal BSS before
any cache disable or writeback operation
- Fix xTaskCreateStaticPinnedToCore() stack size argument in the
spiram_stack test (was passing bytes instead of word count)
- Mark the null-pointer write in func_do_exception() as volatile to
prevent the compiler from optimizing it away
- Extend the [spiram_stack] tests to RISC-V by sharing fibonacci() and
the task/finish helpers across architectures, guarding only the
Xtensa-specific WINDOWBASE/WINDOWSTART prints
If Task WDT is initialised but not start, the call to esp_timer_stop() in
the reconfigure path returns ESP_ERR_INVALID_STATE and reconfiguring the
Task WDT fails. This isn't the case when the Timer Group is used for Task
WDT.
(This failure cascades into the failure due to disabled interrupts, fixed
in the parent commit.)
Signed-off-by: Angus Gratton <angus@redyak.com.au>
- Failures were being masked as function always returned ESP_OK
- In the failure path the spinlock was not unlocked, so interrupts
became permanently disabled.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
Jiang Jiang Jian
Ashish Sharma
Samuel Obuch
Erhan Kurubas
Marius Vikhammer
Michael.B
harshal.patil
Armando (Dou Yiwen)
Song Ruo Jing
Laukik Hase
wuzhenghui
Peter Dragun
sibeibei
Guillaume Souchere
Fu HanxiandCopilot
Angus Gratton
Alexey Lapshin
Alexey Gerenkov
yanzihan@espressif.com
morris