The GDMA layer used `max_data_burst_size == 0` as the only way to disable the
data burst. That conflicts with the upstream drivers' convention where a zeroed
config struct means "unset", so users had no way to ask for the driver default
burst size.
GDMA now treats both 0 and 1 as "no data burst": a single-beat burst has no
benefit over the non-burst mode. The MSPI alignment constraint under Flash
Encryption / PSRAM ECC still takes precedence and is reported with a warning.
The upstream drivers using GDMA now apply their own default burst size (16
bytes) when the user leaves `dma_burst_size` as 0, following the UHCI driver:
- esp_async_crc (AHB / AXI GDMA backend)
- esp_async_memcpy (AHB / AXI / LP-AHB / DW_GDMA backend)
Callers that really want no burst can now set `dma_burst_size` to 1.
Objects with atomic members must not be allocated to PSRAM, otherwise
the ordering guarantee of atomic accesses is weakened due to a hardware
behavior on ESP32 chips. Explicitly request MALLOC_CAP_INTERNAL |
MALLOC_CAP_8BIT for:
- i2c master bus object (atomic status/trans_idx)
- i3c master bus object (atomic fsm)
- ISP processor and AE/AF/AWB/HIST controllers (atomic fsm)
- JPEG decoder/encoder dma2d transaction descriptors (atomic started)
- PPA transaction storage embedding dma2d_trans_t
- dma2d m2m test transaction embedding dma2d_trans_t
Replace *common_components with specific driver dependencies across all
peripheral driver test apps and examples to prevent unnecessary CI
triggers
when common_components change.
This follows the same pattern established in TWAI driver commit:
6d21cc6c29
Changes made:
- 26 component test apps updated
(esp_driver_*/test_apps/.build-test-rules.yml)
- 1 driver test app updated
(components/driver/test_apps/.build-test-rules.yml)
- Key examples updated in examples/peripherals/.build-test-rules.yml
- Established standard dependency pattern: esp_hal_xxx, esp_hw_support,
soc
- Added esp_driver_gpio for GPIO-dependent drivers
