Commit Graph

117 Commits

Author SHA1 Message Date
Wu Zheng Hui
aac7f7ea47 Merge branch 'feat/support_esp32s31_clock_tree_management' into 'master'
feat: support esp32s31 clock tree management

Closes PM-630

See merge request espressif/esp-idf!48934
2026-07-24 20:11:45 +08:00
harshal.patil
a7b29bfda9 change(security): disable Key Manager support on ESP32-C5/P4/S31
The Key Manager hardware peripheral in its current form needs further
design changes before it can be offered as a production feature.
Until a revised peripheral design is available, withdraw ESP-IDF
support for it on all Key Manager capable targets.
2026-07-22 19:58:23 +05:30
wuzhenghui
09253d3f48 feat(esp_security): make esp32s31 on-demand crypto clock management optional 2026-07-22 16:32:46 +08:00
wuzhenghui
a04dc898db feat(esp_security): support s31 security clock management 2026-07-22 16:32:45 +08:00
nilesh.kale
fe18ed97dd feat: added call to aquire clock source for H4 and H21 AES crypto 2026-07-06 10:12:35 +05:30
Mahavir Jain
625ee1abb7 Merge branch 'fix/harden_esp_security' into 'master'
fix(esp_security): harden crypto peripheral error handling

Closes SEC-236, SEC-351, SEC-352, SEC-353, SEC-355, SEC-356, and SEC-357

See merge request espressif/esp-idf!49828
2026-07-03 09:11:33 +05:30
Aditya Patwardhan
36090b7161 feat(esp-tls): Add unified private key interface via esp_key_config_t
Add ESP_KEY_SOURCE_BUFFER and ESP_KEY_SOURCE_PSA key sources so all
hardware backends (DS, ECDSA, secure element) are accessed via PSA
key IDs through a single esp_tls_cfg_t.client_key field.
2026-06-25 11:31:37 +05:30
Ashish Sharma
1b8a365f16 fix(esp_security): harden crypto peripheral error handling 2026-06-19 18:27:22 +08:00
harshal.patil
6b417e9d47 fix(esp_common/esp_fault): make ESP_FAULT_ASSERT survive optimization
ESP_FAULT_ASSERT(C) was silently deleted by the optimizer when C is a cached
flag/status already proven by a preceding `if (!C) return/goto`: the compiler
folds C to a constant and drops all three checks, removing the fault-injection
protection with no warning.
2026-06-17 16:45:29 +05:30
wuzhenghui
69d548c8d1 feat(esp_security): suppoer s31 security clock management 2026-06-10 21:20:04 +08:00
Guillaume Souchere
33e774397c Merge branch 'feat/error-code-registration' into 'master'
feat(esp_common): implement composable error code registration via link-time arrays

Closes IDF-15105 and IDF-15486

See merge request espressif/esp-idf!46125
2026-06-01 09:40:37 +02:00
Guillaume Souchere
d670774f5c feat(esp_common): implement composable error code registration via link-time arrays
Refactor the esp_err_to_name() system to decouple esp_common from
higher-level components. Instead of a monolithic generated table,
each component registers its error codes into a dedicated linker
section (.esp_err_msg_table) via idf_define_esp_err_codes() in its
CMakeLists.txt.

New files:
- tools/err_codes_extract.py: extract ESP_ERR_* defines from headers to CSV
- tools/err_codes_to_c.py: generate C source placing entries into linker section
- tools/err_codes_to_rst.py: generate RST documentation from error codes
- tools/cmake/err_codes.cmake: CMake module providing idf_define_esp_err_codes()
- components/esp_common/include/esp_err_codes.h: esp_err_msg_t typedef
- components/esp_common/src/esp_err_to_name_new.c: new lookup using link-time array
- tools/test_apps/build_system/err_codes_check/: CI test app

Changes:
- Remove all optional component dependencies from esp_common/CMakeLists.txt
- Add .esp_err_msg_table section to all 5 linker scripts
- Register error codes in 18 components via idf_define_esp_err_codes()
- Add new scripts to .gitlab/ci/rules.yml build_check patterns
- use new scripts to generate doc and add CI validation
- Update esp_err.rst to add description of composable code registration
2026-05-28 09:53:32 +02:00
nilesh.kale
fe257f699e feat: enable Secure Boot, Flash Encryption and Key Manager support for S31 2026-05-26 12:57:34 +08:00
nilesh.kale
34e24e1ed3 fix: disable Key Manager and ECDSA TRNG tests for S31 temporarily 2026-05-20 10:17:34 +05:30
nilesh.kale
a530aab0a6 feat: enable key manager and HUK support for S31 2026-05-20 10:17:34 +05:30
Aditya Patwardhan
e9a9091b59 feat(hal): add HMAC and Digital Signature support for esp32s31
Co-authored-by: Nilesh Kale <nilesh.kale@espressif.com>
2026-05-20 10:17:34 +05:30
Chen Jichang
645ff40cde ci(esp32h4): enable ci target test 2026-05-11 16:48:58 +08:00
muhaidong
14e964c0fa fix(esp_security): fix ECDH1 key manager multi-stage helper 2026-05-11 12:03:17 +05:30
Mahavir Jain
bc8db060f1 Merge branch 'feat/key_manager_ecdh1_key_deployment_mode' into 'master'
Key Manager ECDH1 key deployment mode

Closes IDF-15582

See merge request espressif/esp-idf!47988
2026-05-11 09:03:10 +05:30
harshal.patil
9aba184c43 feat(esp_security): add ECDH1 deployment mode to Key Manager driver 2026-04-30 09:29:40 +05:30
harshal.patil
c9366ac4b5 fix(esp_security): Fix the flipped key info slot when deploying a Key Manager-based key 2026-04-30 09:17:38 +05:30
harshal.patil
8ce8d8919b fix(esp_security): Enable ECC clock while using the Key Manager's ECDH key deployment mode 2026-04-30 09:17:31 +05:30
harshal.patil
8bfc4f7255 fix(esp_security): guard key manager APIs against unsupported chip revs
On ESP32-P4 rev < 3.0, Key Manager is software-disabled, but the public
esp_key_mgr.h APIs had no runtime check.
Calls using HMAC/DS/PSRAM key types fell through to
HAL_ASSERT("Unsupported ...") paths in key_mgr_ll.h. Gate
each public API with key_mgr_ll_is_supported() and return
ESP_ERR_NOT_SUPPORTED cleanly instead.
2026-04-27 15:18:34 +05:30
Mahavir Jain
80116d4e07 Merge branch 'feat/add_hmac_support_for_esp32h4' into 'master'
feat: added support for HMAC in ESP32H4

Closes IDF-12257

See merge request espressif/esp-idf!44647
2026-04-15 15:18:03 +05:30
Aditya Patwardhan
bfd3e191bc feat: enable AES, SHA, RSA and ECC support for ESP32S31
Co-authored-by: Nilesh Kale <nilesh.kale@espressif.com>
2026-04-13 10:20:44 +05:30
nilesh.kale
b3243dc6de feat: enable HMAC peripheral support for ESP32-H4 2026-04-09 14:29:57 +05:30
Harshal Patil
876b9581bd Merge branch 'fix/enable_key_mgr_clk_for_efuse_key_ops' into 'master'
Enable Key Manager clock even for efuses-based key operations

See merge request espressif/esp-idf!46740
2026-03-25 21:37:53 +05:30
hebinglin
474d89b4c2 fix(clk): update H21 ECO1 to use 64MHz clock for mspi 2026-03-25 15:38:49 +08:00
harshal.patil
28736a81fa fix(esp_security): Enable Key Manager clocks even for efuse key operations
The Key Manager holds a key usage register, thus, the Key Manager peripheral
clock must be enabled even for efuses-based key operations to route the
crypto operations to correctly to the efuses (default is Key Manager)
2026-03-25 10:38:44 +05:30
harshal.patil
ccc48c3980 fix(esp_security): Fixes incorrect key manager configuration for ESP32-P4 rev < 3 2026-03-24 15:23:23 +05:30
harshal.patil
398d9ea9cd fix(esp_security): Add more validation checks 2026-03-20 11:15:23 +05:30
harshal.patil
0db717b9ec feat(esp_ds): Support using the AES key used by DS peripheral for encrypting params 2026-03-20 11:15:23 +05:30
harshal.patil
5f647c0ba3 docs(key-manager): Add Key-Manager peripheral related documentation 2026-03-18 16:27:39 +05:30
wuzhenghui
51cca0a88f feat(esp_hw_support): support clock tree management for esp32p4 2026-03-04 20:10:54 +08:00
nilesh.kale
0fd1a4c9f8 test(esp_security): re-enable crypto drivers test app for ESP32P4
Also remove common_components dep for security-related tests
2026-02-10 17:48:55 +05:30
harshal.patil
6964de6f45 test(esp_security): Update the Key Manager test to support ESP32-P4 2026-02-10 17:48:52 +05:30
Xiao Xufeng
0a6c922059 fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
This reverts commit 7145fc9558.
2026-01-28 11:15:30 +05:30
igor.udot
4c26ab876b ci: update build-test-rules to use common_components 2026-01-23 10:14:09 +08:00
Aditya Patwardhan
eb4a871eca refactor(esp_hal_security): Updated esp_hal_security build and includes 2026-01-21 10:02:44 +05:30
Song Ruo Jing
215c9993bf fix(clk): update H4 to use 64MHz clock for mspi
And add pll clock ref count
2026-01-04 14:07:01 +08:00
Xiao Xufeng
7145fc9558 Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
This reverts commit 3c5d2e6b58.
2025-12-16 17:43:58 +08:00
C.S.M
0c4cf75c35 feat(esp32s31): Introduce esp32s31 hello world 2025-12-02 10:44:16 +08:00
Harshal Patil
b873a82d5b Merge branch 'feat/generic_key_mgr_key_types' into 'master'
Store key_len field in the key_config

See merge request espressif/esp-idf!42692
2025-11-18 15:12:03 +05:30
C.S.M
961bd0cf78 Merge branch 'feat/introduce_esp32s31' into 'master'
feat(esp32s31): Introduce new target esp32s31

See merge request espressif/esp-idf!43316
2025-11-18 15:55:16 +08:00
harshal.patil
1c1bcf44be feat(esp_security): Support ECDSA-P384 key deployment using Key Manager 2025-11-17 12:34:09 +05:30
harshal.patil
1f2cbde525 change(esp_key_mgr): Store key_len field in the key_info
- Update the Key Manager key types to be generic
- Define a new enum to determine the length of the keys
- Refactor the Key Manager driver support generic key types and key lengths
- Also store key deployment mode in the key recovery info
2025-11-17 12:34:09 +05:30
C.S.M
a90c93541c feat(esp32s31): Introduce new target esp32s31 2025-11-17 14:48:55 +08:00
armando
b25ba4a0c1 ci(p4): disable p4 rev3 invalid tests temporarily 2025-11-17 12:11:39 +08:00
Mahavir Jain
4a53c4e651 Merge branch 'bugfix/esp32c5_encrypted_flash_write_v2' into 'master'
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption

See merge request espressif/esp-idf!43301
2025-11-13 18:01:04 +05:30
Harshal Patil
0debe71b3d Merge branch 'feat/flash_enc_using_key_manager' into 'master'
Support Flash Encryption using Key Manager

Closes IDF-13462 and IDF-14278

See merge request espressif/esp-idf!41879
2025-11-13 07:55:15 +05:30