He Binglin
9c3a6b3f5d
Merge branch 'feat/esp_idf_h4_optimize' into 'master'
...
Feat/esp idf h4 retention and active clk power optimize
Closes PM-746, PM-745, and PM-736
See merge request espressif/esp-idf!48319
2026-05-22 10:55:43 +08:00
hebinglin
2c91b280f4
change(esp_hw_support): disable some periph clk in cpu start
2026-05-21 19:53:51 +08:00
hebinglin
b46b72cf19
feat(esp_hw_support): allow lp io clk close in cpu start
2026-05-21 19:53:51 +08:00
Ondrej Kosta
c7d6c41198
feat(clk_tree): support derived PLL clocks
...
Add a generic derived-PLL clock engine to esp_clk_tree_common that
handles acquire/release, mux selection, and divider programming for
target-defined derived clocks. Per-target descriptors (ESP32-P4,
ESP32-S31) plug into the engine via
esp_clk_tree_get_derived_clk_desc().
2026-05-21 15:59:42 +08:00
armando
f408e1a8bc
feat(sdmmc): add esp32s31 support
...
Enable SDMMC host support on ESP32-S31 across HAL, SOC caps, tests, examples, and documentation.
2026-05-21 09:09:28 +08:00
gaoxu
4e3751b32e
feat(cam): support dvp cam on ESP32-S31
2026-05-14 17:09:49 +08:00
wuzhenghui
3f6957450f
feat(esp_hw_support): support psram PD_TOP retention
2026-05-07 12:02:01 +08:00
wuzhenghui
f1f3f204fe
feat(esp_hw_support): support esp32s31 lightsleep/deepsleep example
2026-05-06 20:15:01 +08:00
hongshuqing
7c665c106c
fix(pmu): update cpll_bbpll_apll_mpll enable config
2026-04-27 14:30:19 +08:00
Marius Vikhammer
5f4161b710
Merge branch 'feature/lockup_debug' into 'master'
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feat(esp_system): add CPU lockup debug support for esp32h4 and esp32s31
See merge request espressif/esp-idf!47630
2026-04-22 17:52:36 +08:00
Marius Vikhammer
8e2b416c38
feat(esp_system): add CPU lockup debug support for esp32h4 and esp32s31
2026-04-22 11:11:02 +08:00
laokaiyao
8d0fca08a0
feat(i2s): support i2s & apll on esp32s31
2026-04-22 09:30:53 +08:00
Chen Ji Chang
83e7b11716
Merge branch 'feat/lcd_use_apll_clock' into 'master'
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refactor(clk_tree): use general api to enable the clk
Closes IDF-11478 and IDF-12972
See merge request espressif/esp-idf!35952
2026-04-20 22:12:01 +08:00
He Binglin
1714d6a2c4
Merge branch 'feat/esp_idfesp32h4_eco1_sleep_support' into 'master'
...
Feat/ESP32H4 ECO1 Sleep Support
Closes PM-633
See merge request espressif/esp-idf!47023
2026-04-20 15:44:19 +08:00
Xorlent
51d059232b
Fix output bit range in bitscrambler documentation
...
Destination bit range incorrect in `Sub-instructions` example
2026-04-17 17:20:28 +08:00
Chen Jichang
6e206dd173
refactor(clk_tree): use general api to enable the clk
2026-04-16 20:03:06 +08:00
hebinglin
4b2e135fd0
feat(esp_hw_support): optimize esp32h4 eco1 active current
2026-04-16 12:10:23 +08:00
wuzhenghui
b913f147ba
feat(esp_hw_support): support esp32s31 esp_clock_output
2026-04-14 12:19:07 +08:00
Song Ruo Jing
50051b74a5
feat(clk): support for esp32s31 clock tree
2026-04-02 20:39:59 +08:00
armando
ebbd9cdb59
feat(psram): support psram device driver
2026-03-31 13:56:43 +08:00
hebinglin
f9078e7538
feat(esp_hw_support): optimize esp32h21 eco1 active current
2026-03-25 15:40:05 +08:00
gaoxu
609a867a91
feat(pmu): h21 eco1 pmu and clk files update
2026-03-25 15:38:49 +08:00
Song Ruo Jing
600bf5b6d7
refactor(esp_hal_regi2c): move regi2c implementation from esp_rom to esp_hal_regi2c
2026-03-10 15:08:51 +08:00
Li Shuai
bdcebfc013
fix(esp_hal_clock): use pmu active/sleep system clock en to control hp root clock
2026-03-05 18:11:17 +08:00
wuzhenghui
5b879a8f58
feat(esp_hw_support): set USB2.0 phy to suspend mode at startup for active power saving
2026-01-28 19:49:46 +08:00
Jiang Jiang Jian
a94c6e8b6b
Merge branch 'bugfix/fix_external_coexistence_depends_on_wifi_connect_issue' into 'master'
...
fix(wifi): fix external coexistence depends on wifi connect issue
Closes WIFI-7123, WIFI-7124, and WIFI-6744
See merge request espressif/esp-idf!43644
2026-01-23 10:56:16 +08:00
muhaidong
cec2bbf0c3
fix(wifi): fix external coexistence depends on wifi connect issue
2026-01-21 17:13:38 +08:00
yanzihan@espressif.com
8ee245afcc
feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32c5
2026-01-20 14:28:35 +08:00
Song Ruo Jing
62511d61e9
refactor(clk): split clock HAL into separate component
2026-01-13 15:50:20 +08:00
