Commit Graph

195 Commits

Author SHA1 Message Date
wuzhenghui
d3c628c759 change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT caps 2026-07-09 17:31:43 +08:00
Marius Vikhammer
d199bb2fa9 Merge branch 'fix/esp_psram_init_fix_v6.0' into 'release/v6.0'
fix(esp_psram): repeated call to init should return invalid state error (v6.0)

See merge request espressif/esp-idf!50274
2026-07-06 16:28:07 +08:00
morris
1c04de442d Merge branch 'feature/psram_halfsleep_mode_support_v6.0' into 'release/v6.0'
feat(psram): allow PSRAM to enter halfsleep mode during light sleep (v6.0)

See merge request espressif/esp-idf!49759
2026-07-03 11:14:20 +08:00
Renz Bagaporo
9debd77118 fix(esp_psram): repeated call to init should return invalid state error
Closes https://github.com/espressif/esp-idf/issues/18722
2026-07-02 09:55:47 +09:00
wuzhenghui
cee20c2f27 feat(esp_psram): wakeup PSRAM by CE# force control instead of dummy write 2026-06-18 11:50:42 +08:00
wuzhenghui
bc55111320 feat(esp_hw_support): check psram data is not corrupted after lightsleep 2026-06-18 11:50:42 +08:00
Song Ruo Jing
33ad4d358a feat(psram): allow PSRAM to enter halfsleep mode during light sleep 2026-06-18 11:50:35 +08:00
Mahavir Jain
77e85b886a docs(esp_psram): clarify carve-out location is at upper end of PSRAM
The previous wording "top of PSRAM" was ambiguous: the carve-out is
actually mapped at the highest physical addresses of PSRAM (after the
rodata, text, and main heap mappings). Update the Kconfig help text for
SPIRAM_ENC_EXEMPT and SPIRAM_ENC_EXEMPT_SIZE, the External RAM
documentation, and the internal layout comment to say "upper end of PSRAM
(highest physical addresses)" instead.
2026-05-21 20:54:31 +05:30
Mahavir Jain
ef7192fc73 feat(esp_psram): add esp_psram_ptr_is_no_enc() helper
Drivers that allocate from the unencrypted PSRAM carve-out via
MALLOC_CAP_SPIRAM_NO_ENC currently have no way to verify after the fact
which pool a buffer came from. This is particularly relevant for callers
using heap_caps_malloc_prefer(MALLOC_CAP_SPIRAM_NO_ENC, MALLOC_CAP_SPIRAM),
where a silent fallback to encrypted PSRAM would still pass the typical
esp_ptr_external_ram() check.

Expose esp_psram_ptr_is_no_enc() in the public esp_psram.h header. It
performs a range check against the carve-out's virtual-address window and
returns false when PSRAM is not initialized or CONFIG_SPIRAM_ENC_EXEMPT is
disabled, so callers do not need to guard the call site with #if.

Also reference the helper from the External RAM documentation alongside
the heap_caps_malloc(MALLOC_CAP_SPIRAM_NO_ENC) usage example.
2026-05-21 20:54:31 +05:30
Mahavir Jain
5c28d2a597 fix(esp_psram): handle carve-out vaddr exhaustion and add region to self-test
If the virtual-address pool is exhausted when reserving the unencrypted
PSRAM carve-out (the warning at L388 may already have fired for the main
mapping), esp_mmu_map_reserve_block_with_caps() returns an error rather
than aborting. Convert the previous assert() into a logged fallback that
disables the carve-out for this boot, mirroring the SPIRAM_ENC_EXEMPT_SIZE
>= psram_available_size path.

Also extend esp_psram_extram_test() to run the standard memory test on
the carve-out region when CONFIG_SPIRAM_ENC_EXEMPT is enabled, so the
unencrypted mapping is exercised on startup like the other PSRAM regions.
2026-05-21 20:54:31 +05:30
harshal.patil
d1d45ff256 change(esp_psram): Consider all PSRAM regions in PMP protection 2026-05-21 20:54:30 +05:30
Mahavir Jain
10d2d9cb9f docs(esp_psram): document MALLOC_CAP_SPIRAM_NO_ENC carve-out
Extends the External RAM encryption section to describe
CONFIG_SPIRAM_ENC_EXEMPT and the MALLOC_CAP_SPIRAM_NO_ENC heap
capability, including a security warning and a typical DMA-alignment
use case. Mirrors the change in zh_CN.
2026-05-21 20:54:30 +05:30
Mahavir Jain
e7cd4a1500 feat(esp_psram): add option to carve unencrypted PSRAM region
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
2026-05-21 20:54:30 +05:30
Xiao Xufeng
475ec39cb4 fix(mspi): fixed possible boot failure in some builds when psram is enabled
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
2026-05-15 17:31:37 +08:00
Chen Jichang
d1a64bffc0 refactor(clk_tree): use general api to enable the clk 2026-05-15 13:55:37 +08:00
Marius Vikhammer
d09e551417 docs: clarify PSRAM default allocation behavior
Clarify that MALLOC_CAP_DEFAULT describes a memory capability
rather than the malloc() placement policy, so PSRAM-backed
capability allocations are documented correctly when malloc()
remains internal-only by default.

Closes https://github.com/espressif/esp-idf/issues/18391

Made-with: Cursor
2026-03-27 10:05:28 +08:00
igor.udot
e2a8bbe639 ci: update build-test-rules to use common_components 2026-03-20 15:53:26 +08:00
Song Ruo Jing
c7ae253b89 feat(mspi): support 120MHz flash and psram for esp32c61 2026-03-19 14:30:46 +00:00
Xiao Xufeng
248d80319c fix(psram): cleanup PSRAM_MSPI_MB_WORKAROUND to avoid future issue 2026-02-05 01:19:28 +08:00
Michael (XIAO Xufeng)
e24fbebd27 Merge branch 'change/change_to_only_do_v2p_once_when_startup_v6.0' into 'release/v6.0'
mmu: no longer disable cache when converting virtual addr to physical addr and vice versa (v6.0)

See merge request espressif/esp-idf!45474
2026-01-30 15:53:09 +08:00
Jiang Jiang Jian
d3e1887bbc Merge branch 'fix/p4_min_rev_usage_v6.0' into 'release/v6.0'
P4: fix wrong rev_min usage in rom and other places (v6.0)

See merge request espressif/esp-idf!45223
2026-01-30 10:50:51 +08:00
Xiao Xufeng
79f7427729 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-28 21:46:00 +08:00
armando
165ecbab44 test(mspi): add flash api run on psram stack test for xip_psram case 2026-01-28 15:30:15 +08:00
armando
aa8dc66225 fix(psram): fixed requirement on esp_driver_gpspi on esp32 2026-01-20 11:14:40 +08:00
armando
f2b715937f fix(mspi): fixed mspi dma burst timing issue 2026-01-15 14:08:53 +08:00
Xiao Xufeng
21a6b1a5be fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on ESP32-C5 v1.2 and C61 v1.1 2026-01-09 10:27:28 +08:00
wanckl
d12f941787 feat(driver_spi): split spi hal component 2025-12-16 20:38:09 +08:00
Song Ruo Jing
62899cbba6 refactor(gpio): split GPIO HAL into separate component
cleaned up some includes in GPIO peripheral files
2025-12-08 14:33:26 +08:00
Alexey Gerenkov
d8e47c5e43 Merge branch 'feature/dynamic_flags_in_toolchain_cmake_v6.0' into 'release/v6.0'
feat(build): propagate compiler flags from files to toolchain.cmake (v6.0)

See merge request espressif/esp-idf!43499
2025-11-21 16:19:34 +08:00
morris
f229575f98 Merge branch 'change/psram_200m_as_default_v6.0' into 'release/v6.0'
psram: use 200MHz as default on p4 (v6.0)

See merge request espressif/esp-idf!43442
2025-11-19 15:14:03 +08:00
Alexey Lapshin
a217630b1e feat(build): propagate compiler flags from files to toolchain.cmake
This change improves build consistency across external projects integrated
through CMake by ensuring that compiler flags defined in configuration files
are passed correctly to the toolchain. It covers the majority of use cases,
as external projects are typically also CMake-based. For projects that use
a custom build system, users will still need to specify the required flags
manually.
2025-11-19 01:12:40 +07:00
Jiang Jiang Jian
d891c55045 Merge branch 'bugfix/psram_mmap_for_all_targets_v6.0' into 'release/v6.0'
fix(esp_psram): make SPIRAM_USE_MEMMAP available for all targets (v6.0)

See merge request espressif/esp-idf!43131
2025-11-18 12:27:36 +08:00
armando
04a711b00b change(psram): use 200M as default 2025-11-18 11:04:47 +08:00
Armando
c26ed5dba0 feat(psram): support 250MHz in experimental 2025-11-14 09:34:01 +08:00
armando
1f7b1f3615 feat(mspi): supported psram & flash 120MHz timing tuning 2025-11-06 02:20:48 +00:00
Mahavir Jain
2b82146902 fix(esp_psram): make SPIRAM_USE_MEMMAP available for all targets
This reverts earlier commit d2858847 and thereby making SPIRAM_USE_MEMMAP
available for all targets.

This config option has no direct usage but just avoids adding the PSRAM
to heap but still keeps it memory mapped.

Closes https://github.com/espressif/esp-idf/issues/17764
2025-11-05 14:07:09 +05:30
armando
9fadbf2588 fix(psram): fixed p4 rev3 xip stuck after board reset issue 2025-10-20 03:09:47 +00:00
Chen Chen
a4710cc206 refactor(driver): remove redundant driver dependencies
now the driver component only contains legacy code for i2c, twai and
touch sensor
2025-09-30 15:47:45 +08:00
C.S.M
b145ede835 refactor(mspi): Make mspi hal layer independent 2025-09-26 14:57:54 +08:00
Marius Vikhammer
484d2c5c2f fix(system): fixed issues with unused variable warnings when compiling with NDEBUG 2025-09-19 15:42:07 +08:00
Alexey Lapshin
9281e78381 change(esp_libc): rename newlib component to esp_libc 2025-09-09 22:00:44 +08:00
armando
ad4fe4c394 fix(psram): fixed psram cross page issue 2025-08-21 09:57:07 +08:00
Mahavir Jain
d2858847b2 fix(esp_psram): make SPIRAM_USE_MEMMAP depend on ESP32 target 2025-08-11 18:06:11 +05:30
Mahavir Jain
54c7803cd3 fix(psram): provide boot warning about PSRAM encryption issue on C5/C61
For C5/C61 revision 1.0, PSRAM encryption has hardware issue. This will
be addressed in future silicon version. Add explicit warning about this.
2025-08-11 18:06:11 +05:30
armando
9be8dccef5 feat(psram): psram support on h4 2025-07-28 10:16:48 +08:00
armando
73113c0ce8 change(psram): change logw to logd 2025-06-25 06:45:33 +00:00
armando
954e88c92d feat(psram): support fallback to use default driver pattern when id isn't match 2025-06-19 09:31:48 +08:00
armando
7a6cd632c5 fix(psram): fixed psram ptr check under xip_psram condition
Closes https://github.com/espressif/esp-idf/pull/15999
Closes https://github.com/espressif/esp-idf/issues/15997
2025-06-06 10:11:32 +08:00
John Boiles
0e680775f9 fix(memory-utils): Add _instruction_reserved_start/end to esp_psram_check_ptr_addr
Adds missing range check that can be used when SPIRAM_XIP_FROM_PSRAM is enabled.
2025-06-06 10:11:32 +08:00
armando
412b79ed1c change(psram): limited 2t check only for ap 2025-05-26 17:06:03 +08:00