Introduced in 8818157e42
The workaround in the commit routes the signal to LP GPIO matrix first.
When uses LP IOMUX pin as UART RX, the signal did not bypass the matrix,
which caused the issue.
This commit adds rtc_gpio_iomux_input and rtc_gpio_iomux_output APIs
to align with existing GPIO driver APIs.
Treat ESP_INTR_FLAG_SHARED_PRIVATE as shared when selecting interrupt
lines and avoid misclassifying private shared vectors as non-shared
during free. Also fix two error-path leaks in esp_intr_alloc_info by
freeing the temporary handle and rolling back group_name on allocation
failure.
refactor(esp_hw_support): add semantic vector descriptor helpers
Introduce helper macros to classify vector descriptor state (shared,
non-shared, private shared, and uninitialized) and apply them in
allocator/free/dump paths. This makes private-shared semantics explicit
and reduces repeated bitwise checks.
Rename vector descriptor helpers to explicitly distinguish public
shared, private shared, and shared-family states. This improves
readability and avoids ambiguity when handling mixed shared/non-shared
flag combinations.
Replace *common_components with specific driver dependencies across all
peripheral driver test apps and examples to prevent unnecessary CI
triggers
when common_components change.
This follows the same pattern established in TWAI driver commit:
6d21cc6c29
Changes made:
- 26 component test apps updated
(esp_driver_*/test_apps/.build-test-rules.yml)
- 1 driver test app updated
(components/driver/test_apps/.build-test-rules.yml)
- Key examples updated in examples/peripherals/.build-test-rules.yml
- Established standard dependency pattern: esp_hal_xxx, esp_hw_support,
soc
- Added esp_driver_gpio for GPIO-dependent drivers
The following updates have been made in this commit:
- The commit places FreeRTOS code in flash memory by default.
- CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH has been removed.
- CONFIG_FREERTOS_IN_IRAM is unhidden and can be used to restore the
previous memory placement.
- A test has been added for users to conduct performance impact testing
based on memory placement configurations.
