The skipif marker on test_rtc_fast_reg2_execute_violation evaluates
config.getvalue("target"), but in CI pytest is invoked by parametrized
node-id with no --target option, so the predicate is never true and the
test is not skipped on esp32c5/esp32c6/esp32h2/esp32p4. These targets have
no PMS peripheral case for executing from RTC-fast memory, so they raise a
generic "Illegal instruction" panic instead of the "Memory protection
fault" the test expects, and fail on every run.
Replace skipif with the temp_skip marker (already done on master in
288fc561b7). The idf_pytest plugin evaluates temp_skip against the
parametrized target, so these targets are skipped correctly. esp32c3 and
esp32s2 keep running, as they do raise a real memory protection fault.
Closes IDFCI-8848
Closes IDFCI-10459
Co-authored-by: Hrushikesh Bhosale <hrushikesh.bhosale@espressif.com>
Squashes these original commits for release/v5.4 backport traceability:
- 9b289dc5ad6 ci: apply idf-ci 1.x
- 381df980d57 ci: remove pip-cache and other unused jobs
- 32375a0a15e ci: apply common-scripts CI refactor
- Disable test_cli_installer_win (when: never), matching release/v5.5
- Download known-failure cases and pass --ignore-result-files on Windows build-system pytest
- Force Ninja response files on Windows hosts via CMAKE_NINJA_FORCE_RESPONSE_FILE in utilities.cmake (backport of 2e5d930e)
Co-authored-by: Cursor <cursoragent@cursor.com>
Backport of !49288 to release/v5.4 (cmake@3.16.3).
Adapted for release/v5.4:
- Linux/macOS jobs added in .gitlab/ci/build.yml (build-system pytest
lives there on v5.4, not host-test.yml).
- Known-failure download uses get_known_failure_cases_file.py.
- macOS jobs keep .before_script:build:macos / macos_shell tags.
- Windows minimal-cmake job follows v5.4 install/tags conventions.
- Skip test_idf_qemu on Windows (pexpect.spawn unavailable).
Co-authored-by: Cursor <cursoragent@cursor.com>
ECDSA based Secure Boot V2 is not functional for certain input vectors on
ESP32-C5/C61/H2/P4 and on the preview targets ESP32-H4/H21. RSA based Secure
Boot V2 is the recommended scheme where the SoC supports it. This issue will be
fixed in a future hardware ECO revision; more details will be shared through the
hardware errata document.
A new hidden Kconfig option SECURE_BOOT_V2_ECDSA_INSECURE marks the affected
mass-production SoCs (ESP32-C5/C61/H2/P4). On these SoCs, when hardware Secure
Boot V2 is enabled, the ECDSA (V2) signing scheme is no longer offered by
default; it must be turned on explicitly via SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
under "Allow potentially insecure options" (CONFIG_SECURE_BOOT_INSECURE). App
signing without hardware Secure Boot is not affected. Note that ESP32-C61 has no
RSA based Secure Boot V2, so it has no Secure Boot scheme enabled by default.
The preview targets ESP32-H4 and ESP32-H21 mark ECDSA Secure Boot V2 as not
supported in their SoC capabilities instead of using the option above. As
ESP32-H4 has no other Secure Boot V2 scheme, Secure Boot is disabled entirely on
it; ESP32-H21 retains RSA based Secure Boot V2.
The security documentation keeps the ECDSA Secure Boot V2 content visible and
adds a warning describing the limitation (including that ECDSA Secure Boot V2 on
ESP32-C61 is not recommended for production). CI apps that exercise ECDSA Secure
Boot V2 on the affected SoCs set CONFIG_SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
accordingly.
Replace argparse with rich-click and use esp_pylib.logger for
standardized console output and fatal error handling.
(cherry picked from commit 3a7896f2c5)
Co-authored-by: zhanghaipeng <zhanghaipeng@espressif.com>
Move the OpenCode companion guide into the ble_uart_service example.
Add English and Chinese Markdown guides with image assets.
Keep ESP-BLE-UART naming consistent across the example and bridge tooling.
(cherry picked from commit 926111e721)
Co-authored-by: Zhou Xiao <zhouxiao@espressif.com>
PMP entry 3 (SOC_DROM_MASK_HIGH, TOR mode) in the memprot path
was incorrectly granted RW permission on esp32h21 and esp32c61.
The mask ROM data region is inherently read-only; remove the W bit.
Also added necessary tests to check voilations and re-enabled
tests for ESP32P4
