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36,223 Commits 25 Branches 192 Tags
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Commit Graph
551 Commits
Author SHA1 Message Date
Jiang Jiang Jian 8775d06702 Merge branch 'fix/fix_tsens_power_after_modem_wakeup_v5.2' into 'release/v5.2' 
fix(esp_hw_support): fix tsensor power enable failed after modem state wakeup (v5.2)

See merge request espressif/esp-idf!36226
 2025-01-16 20:30:54 +08:00
Xiao Xufeng e9d35ac8ac feat(soc): add Kconfig rev min option and increase max ver for H2 v1.2 2025-01-16 00:18:20 +08:00
Michael (XIAO Xufeng) a83eb05dc0 Merge branch 'feat/increase_c2_supported_ver_v5.2' into 'release/v5.2' 
feat(soc): increase c2 max supported version (v5.2)

See merge request espressif/esp-idf!35972
 2025-01-15 15:25:56 +08:00
wuzhenghui aaf7c6a9ce fix(esp_hw_support): fix modem power enable failed after modem state wakeup 2025-01-09 11:12:51 +08:00
Michael (XIAO Xufeng) b3b14bdf43 Merge branch 'bugfix/warn_rc32k_use_in_kconfig_v5.2' into 'release/v5.2' 
fix(clk): add an inevitable kconfig option to be selected to use rc32k (v5.2)

See merge request espressif/esp-idf!35966
 2025-01-07 15:49:51 +08:00
Marius Vikhammer 94d9ab88bb fix(interrupt): fixed wrongly reserved interrupt for wifi on H2 2025-01-02 16:49:11 +08:00
Xiao Xufeng 526aef42cc feat(soc): increase c2 max supported version 2024-12-25 20:30:42 +08:00
Song Ruo Jing 47c9382cc2 fix(clk): add an inevitable kconfig option to be selected to use rc32k 2024-12-25 20:07:26 +08:00
Song Ruo Jing 54ca0cf944 fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2 rtc_clk_cpu_freq_set_xtal behavior to other chips
 2024-12-24 22:29:14 +08:00
Li Shuai a87c6408ec fix(esp_hw_support): fix the issue of regdma wait node to immediately return to done 2024-12-03 10:35:43 +08:00
Jiang Jiang Jian d917fa42c9 Merge branch 'bugfix/chip823_pll_low_temp_bug_v5.2' into 'release/v5.2' 
[H2]Fix cpu switch fail for bbpll cali fail bug in low temp (v5.2)

See merge request espressif/esp-idf!34600
 2024-11-15 16:29:39 +08:00
Jiang Jiang Jian 5c07af3ed7 Merge branch 'fix/fix_ota_slowclock_switching_v5.2' into 'release/v5.2' 
fix(esp_hw_support): fix rtc slow clock missing after the OTA app changes the slow clock source (v5.2)

See merge request espressif/esp-idf!34472
 2024-11-12 19:25:47 +08:00
hongshuqing 45bb984dcd fix: fix pll low temp bug 2024-11-08 12:02:38 +08:00
wuzhenghui 9085e0737f fix(esp_hw_support): enable all supported slow clock at pmu_init 2024-10-28 12:09:12 +08:00
hongshuqing 9c999628ba fix(h2): modify wrong lslp drvb config 2024-10-18 17:01:09 +08:00
Jiang Jiang Jian e038e66620 Merge branch 'bugfix/fix_s3c3_wrong_ext32k_config_bug_v5.2' into 'release/v5.2' 
fix(ext_32k): fix the external 32K issue on C3&S3 (v5.2)

See merge request espressif/esp-idf!33157
 2024-10-17 10:46:10 +08:00
wuzhenghui 6a35be4e47 change(esp_hw_support): switch hp_sys default power mode with clock src selection 2024-10-11 15:47:48 +08:00
morris 73302ca332 Merge branch 'bugfix/warn_rc32k_use_v5.2' into 'release/v5.2' 
fix(clk): warn the users to avoid using RC32K clock (v5.2)

See merge request espressif/esp-idf!33502
 2024-10-09 17:02:54 +08:00
Song Ruo Jing 6594e71d2d fix(clk): warn the users to avoid using RC32K clock 2024-09-13 11:59:58 +08:00
Jiang Guang Ming d2e04a987b feat(esp_hw_support): Support esp32c2 rev2.0 chip 2024-09-10 10:07:31 +08:00
zlq 4d9aa7fd25 fix(ext_32k): fix the external 32K issue on C3&S3 (v5.2) 2024-09-04 14:57:55 +08:00
laokaiyao bff6fb518e refactor(bootloader): lower down the log level to reduce the bootloader size 2024-08-28 12:12:56 +08:00
laokaiyao e5393c6e2e feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-28 12:12:54 +08:00
Xiao Xufeng 1a111187fa fix(startup): move rtc initialization before MSPI timing tuning to improve stability 2024-08-15 20:55:11 +08:00
wuzhenghui 4ddeee6260 fix(esp_hw_support): wait eFuse controller idle after sleep wakeup 2024-07-08 14:14:57 +08:00
Jiang Jiang Jian 88c6cf5cfa Merge branch 'feature/esp32c6_pu8m_in_sleep_support_v5.2' into 'release/v5.2' 
feat(sleep): support 8m force pu in sleep for esp32c6 & esp32h2 (v5.2)

See merge request espressif/esp-idf!31000
 2024-07-01 10:43:28 +08:00
Island 1491b579a8 Merge branch 'bugfix/fix_some_ble_bugs_cjh_v5.2' into 'release/v5.2' 
Fixed some BLE bugs 240620 (backport v5.2)

See merge request espressif/esp-idf!31647
 2024-06-26 20:33:19 +08:00
chenjianhua 8334a10f6d fix(bt): Update bt lib for ESP32-C3 and ESP32-S3(eca46a0) 
- Fixed adv data buffer free after restart adv
- Fixed BLE interrupt allocation using esp API
 2024-06-25 00:04:14 +08:00
wuzhenghui 851c176d1b change(esp_hw_support): update xtal_freq after assume to avoid mass print in DFS 2024-06-24 13:38:10 +08:00
morris b63fd4eaee Merge branch 'feature/uart_sleep_retention_support_v5.2' into 'release/v5.2' 
feat(uart): support uart module sleep retention on c6/h2 (v5.2)

See merge request espressif/esp-idf!31008
 2024-06-19 14:59:30 +08:00
Song Ruo Jing 707aebc607 feat(uart): support uart module sleep retention on c6/h2 2024-06-18 15:04:20 +08:00
Li Shuai ab595d8d08 fix(esp_hw_support): use iterator for regdma_link_stats to save stack consume 
Closes https://github.com/espressif/esp-idf/issues/13288
 2024-06-17 15:55:46 +08:00
wuzhenghui 92e3fd4e44 change(esp_hw_support/sleep): improve esp32c3 systimer stall bug workaround 2024-06-04 21:30:28 +08:00
Omar Chebib 742b3a1814 fix(esp_hw_support): clear reserved interrupts that are not applicable for each target 2024-05-30 12:12:44 +08:00
Omar Chebib 35dd4e1557 refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC 2024-05-30 11:49:13 +08:00
chaijie@espressif.com 15e9809b67 feat(sleep): support 8m force pu in sleep for esp32c6/esp32h2 2024-05-22 11:35:06 +08:00
Li Shuai 0e28063291 change(esp_hw_support): dump sleep retention context to io stream 2024-04-22 12:49:34 +08:00
Li Shuai 9c8b54b886 change(esp_hw_support): use new retention api to implement gdma retention 2024-04-22 12:49:33 +08:00
wuzhenghui 8f896f07c5 fix(esp_hw_support): fix pmu power domain initialize order 2024-04-10 10:10:13 +08:00
Laukik Hase 17ffe58051 fix(esp_hw_support): Fix the flash I/DROM region PMP protection 2024-04-03 15:48:46 +05:30
Li Shuai 2d0ac9208e fix(esp_hw_support): fixed modem hang caused by incorrect configuration of power and isolate signals 2024-04-03 10:43:13 +08:00
Jiang Jiang Jian 08299f5f9b Merge branch 'bugfix/fix_maximum_value_of_config_rtc_clk_cal_cycles_bug_v5.2' into 'release/v5.2' 
ESP All Chip: fixed the maximum value of config RTC_CLK_CAL_SYCLES bug (v5.2)

See merge request espressif/esp-idf!29648
 2024-03-15 11:10:38 +08:00
hongshuqing 7771d72d7c fix: fix_maximum_value_of_config_rtc_clk_cal_cycle_bug 2024-03-14 16:11:20 +08:00
chaijie@espressif.com c7660fe26d fix: fix sleep fast_mem & slow_mem may lost bug 2024-03-14 15:03:41 +08:00
Laukik Hase 68442ecaa0 refactor(esp_hw_support): Remove redundant PMP entry for ROM region 
- The ROM text and data sections share the address range
    (see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
  - Initially, we had two PMP entries for this address range - one marking the
    region as RX and the other as R.
  - However, the latter entry is redundant as the former locks the PMP settings.
  - We can divide the ROM region into text and data sections later when we
    define boundaries marking these regions from the ROM.
 2024-03-01 10:25:07 +05:30
Laukik Hase a56fc41215 fix(esp_hw_support): Fix the I/DCACHE region PMP protection 2024-03-01 10:25:07 +05:30
hongshuqing b3a73d5b63 feat(pmu): set fix voltage to different mode for esp32c6 2024-02-22 14:49:01 +08:00
Jiang Jiang Jian 3c7c5829b7 Merge branch 'h2_auto_dbias_master_hsq_v5.2' into 'release/v5.2' 
ESP32H2: Active & sleep dbias get from efuse to fix the voltage (v5.2)

See merge request espressif/esp-idf!28714
 2024-02-21 10:49:16 +08:00
wuzhenghui 2cd8335818 feat(esp_hw_support): support gdma register context sleep retention 2024-02-18 15:57:15 +08:00
Mahavir Jain e173895618 fix(soc): change debug addr range to CPU subsystem range 
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).

For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.

For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
 2024-01-29 13:57:04 +08:00