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49,165 Commits 24 Branches 184 Tags
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1676 Commits

Author SHA1 Message Date
morris
da14c42596 Merge branch 'fix/esp32_flash_cache_crash_v6.0' into 'release/v6.0' 
fix(hw_support): Fix crash when reconfiguring flash from 40 to 80 MHz on ESP32 (v6.0)

See merge request espressif/esp-idf!44898
 2026-02-01 10:20:19 +08:00
Song Ruo Jing
89da3742b8 refactor(clk): split clock HAL into separate component 2026-01-31 22:32:37 +08:00
Mahavir Jain
78464dfab7 Merge branch 'refactor/create_esp_hal_security_v6.0' into 'release/v6.0' 
refactor: Created esp_hal_security component (v6.0)

See merge request espressif/esp-idf!45349
 2026-01-31 10:28:48 +05:30
Mahavir Jain
ee2da28726 Merge branch 'feat/esp_tee_backports_v6.0' into 'release/v6.0' 
feat(esp_tee): Feature/fixes backports to `release/v6.0`

See merge request espressif/esp-idf!45095
 2026-01-31 10:27:34 +05:30
Aditya Patwardhan
4d3cfefc2e refactor(esp_hal_security): Updated esp_hal_security build and includes 2026-01-30 17:12:54 +05:30
morris
799e366cee Merge branch 'feat/esp_driver_dma_v6.0' into 'release/v6.0' 
feat(dma): graduate the dma driver from esp_hw_support to esp_driver_dma (v6.0)

See merge request espressif/esp-idf!45387
 2026-01-30 12:40:39 +08:00
Jiang Jiang Jian
d3e1887bbc Merge branch 'fix/p4_min_rev_usage_v6.0' into 'release/v6.0' 
P4: fix wrong rev_min usage in rom and other places (v6.0)

See merge request espressif/esp-idf!45223
 2026-01-30 10:50:51 +08:00
morris
db750dc1a0 feat(dma): graduate the dma driver from esp_hw_support to esp_driver_dma 2026-01-29 14:41:14 +08:00
Laukik Hase
421246323a feat(esp_tee): Add support for the RISC-V H/W stack guard mechanism 2026-01-29 11:49:14 +05:30
Jiang Jiang Jian
b18f302fe6 Merge branch 'feat/freq_change_enc_write_c5' into 'release/v6.0' 
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" (v6.0)

See merge request espressif/esp-idf!45166
 2026-01-29 10:19:51 +08:00
Xiao Xufeng
79f7427729 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-28 21:46:00 +08:00
Xiao Xufeng
29587bb50a fix(esp32p4): fix rom and ld misuse min_rev 2026-01-28 21:42:03 +08:00
Jiang Jiang Jian
b34e8b03b9 Merge branch 'fix/fix_secure_boot_fast_wake_feature_v6.0' into 'release/v6.0' 
fix(esp_system): fix ROM secure boot fast wake feature (v6.0)

See merge request espressif/esp-idf!44951
 2026-01-28 17:50:30 +08:00
Jiang Jiang Jian
ea33171ec8 Merge branch 'feat/support_configurable_behavior_for_sleep_console_v6.0' into 'release/v6.0' 
feat(esp_hw_support): Support configurable console uart behavior before sleep (v6.0)

See merge request espressif/esp-idf!44949
 2026-01-28 17:50:23 +08:00
Xiao Xufeng
32e4e83f84 Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit cca0ac8c56.
 2026-01-15 23:44:05 +08:00
Xiao Xufeng
206274d298 refactor(startup): make flash_init_state static 2026-01-13 18:01:32 +08:00
Mattias Schäffersmann
5faff98cc5 fix(hw_support): Fix crash when reconfiguring flash from 40 to 80 MHz 
Reading from the flash while it is being reconfigured leads to data
corruption and a crash when the reconfiguration code is located in flash.
This is only an issue if a device has a bootloader that runs with 40 MHz
flash and an application flashed via OTA that runs with 80 MHz flash.
If bootloader and application run with the same flash speed, the
reconfiguration is basically a no-op and no data corruption occurs.
Fix reconfiguration by placing the code back into IRAM.

Issue introduced in: 7549d08

Closes: https://github.com/espressif/esp-idf/pull/17905
 2026-01-13 18:01:32 +08:00
Jiang Jiang Jian
12d0df2537 Merge branch 'bugfix/fix_pvt_after_sleep_v6.0' into 'release/v6.0' 
fix(pvt): fix pvt retention bug,replace pvt_retention with pvt_init

See merge request espressif/esp-idf!44927
 2026-01-12 15:38:56 +08:00
zlq
1d41de96d8 fix(pvt): fix pvt retention bug,replace pvt_retention with pvt_init 2026-01-09 15:44:53 +08:00
wuzhenghui
c17787722c docs(esp_system): add detailed RTC memory layout documentation 2026-01-09 11:15:15 +08:00
wuzhenghui
9a20ef85f5 fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21 2026-01-09 11:15:12 +08:00
wuzhenghui
a7f002c37e feat(esp_hw_support): add test case for esp_sleep_set_uart_handling 2026-01-09 11:09:03 +08:00
Jiang Jiang Jian
8afaa70921 Merge branch 'bugfix/c5_add_freq_restriction_again_v6.0' into 'release/v6.0' 
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v6.0)

See merge request espressif/esp-idf!44499
 2026-01-09 10:21:02 +08:00
Jiang Jiang Jian
8d0fc97530 Merge branch 'bugfix/idfgh-16634_v6.0' into 'release/v6.0' 
backport v6.0: remove the configurable constraint for sleep memory usage optimization option

See merge request espressif/esp-idf!44754
 2026-01-08 13:49:39 +08:00
Song Ruo Jing
ce475d901d refactor(uart): split UART HAL into separate component 2026-01-04 16:02:57 +08:00
Li Shuai
0335029a7b fix(ld): fix cannot move location counter backwards (from 3fc88000 to 3fc87fff) 2026-01-04 10:44:33 +08:00
Marius Vikhammer
da1829ed25 fix(system): removed the exe flag from psram memory for esp32 
extern_ram_seg segment was marked as RWX in the linker script
even though we cannot run code from PSRAM on ESP32.

This is a link-time check, and actual CPU RWX permissions are
controlled seperately so this has no practical implications,
but it could mistakenly be remarked upon during security scans
or checks by customers.
 2025-12-29 16:39:01 +08:00
Xiao Xufeng
cca0ac8c56 fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption 
This reverts commit 7145fc9558.
 2025-12-24 02:31:42 +08:00
Mahavir Jain
7da79a653c Merge branch 'feature/mbedtls_psa_migration_v6.0' into 'release/v6.0' 
feat(mbedtls): PSA Migration to release v6.0

See merge request espressif/esp-idf!43323
 2025-12-21 13:52:48 +05:30
Jiang Jiang Jian
f409428bf3 Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0' 
fix(spi_flash): Add CPU frequency switching during flash encrypted write (v6.0)

See merge request espressif/esp-idf!44304
 2025-12-21 15:28:33 +08:00
Jiang Jiang Jian
ac1e81f980 Merge branch 'fix/esp32p4_eco5_multicore_wfi_autoclock_gating_v6.0' into 'release/v6.0' 
fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore (v6.0)

See merge request espressif/esp-idf!44255
 2025-12-21 15:22:15 +08:00
Ashish Sharma
f306dbea84 feat(mbedtls): migrates ESP-TEE with PSA APIs 2025-12-19 07:28:33 +08:00
Xiao Xufeng
469953bd04 Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit 3c5d2e6b58.
 2025-12-17 01:21:46 +08:00
Xiao Xufeng
ae7124abe3 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 01:21:45 +08:00
Chen Chen
1b015d22eb refactor(esp_system): clear dependency on hal components 2025-12-16 09:11:59 +08:00
Samuel Obuch
5908c9574c fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore 2025-12-15 14:47:54 +01:00
morris
5c5d78b639 Merge branch 'ci/freertos_header_v6.0' into 'release/v6.0' 
ci(header_check): Add check for public header should not include freertos  (backport v6.0)

See merge request espressif/esp-idf!44104
 2025-12-11 18:00:57 +08:00
morris
946dcf73e3 Merge branch 'feature/graduate_i2s_parlio_analog_hal_components_v6.0' into 'release/v6.0' 
Feature/graduate i2s parlio analog hal components v6.0

See merge request espressif/esp-idf!44043
 2025-12-11 16:58:37 +08:00
Jiang Jiang Jian
3df1ee13fb Merge branch 'fix/fix_mspi_write_stuck_after_reset_v6.0' into 'release/v6.0' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v6.0)

See merge request espressif/esp-idf!43994
 2025-12-11 13:59:25 +08:00
laokaiyao
e964c74618 feat(hal): graudate the parlio hal driver into a new component 2025-12-11 10:26:05 +08:00
laokaiyao
73ebd544fd refactor(i2s): refactor of the private i2s caps 2025-12-11 10:25:42 +08:00
C.S.M
ed64e7bf78 ci(header_check): Add check for public header should not include freertos 2025-12-10 15:10:43 +08:00
morris
37c614d626 feat(twai): graduate the hal drivers into esp_hal_twai component 2025-12-10 13:56:47 +08:00
wuzhenghui
01ec965252 fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-10 12:21:55 +08:00
morris
4ca7b95d83 Merge branch 'refactor/esp_hal_gpio_v6.0' into 'release/v6.0' 
refactor(gpio): split GPIO HAL into separate component (v6.0)

See merge request espressif/esp-idf!43895
 2025-12-09 16:02:49 +08:00
Alexey Gerenkov
effa1e4248 Merge branch 'feature/update-toolchain-to-esp-15.2.0_20250929.4-6d3fdb7_v6.0' into 'release/v6.0' 
Make Picolibc the default libc (v6.0)

See merge request espressif/esp-idf!43966
 2025-12-08 18:13:08 +08:00
Song Ruo Jing
62899cbba6 refactor(gpio): split GPIO HAL into separate component 
cleaned up some includes in GPIO peripheral files
 2025-12-08 14:33:26 +08:00
Jiang Jiang Jian
c33b848fea Merge branch 'bugfix/fix_chip_hangup_v6.0' into 'release/v6.0' 
bugfix: clear regdma status when restart V6.0

See merge request espressif/esp-idf!43908
 2025-12-08 11:07:25 +08:00
Alexey Lapshin
ad7f4b9670 feat(esp_libc): make picolibc default libc 2025-12-06 00:08:35 +07:00
morris
0e6525a97c Merge branch 'bugfix/uart_related_backports_v6.0' into 'release/v6.0' 
fix(uart): some related uart backports (v6.0)

See merge request espressif/esp-idf!43612
 2025-12-02 17:40:25 +08:00