CMakev2's DEFERRED mode for idf_component_optional_requires only links
optional components already present in the dependency graph. This caused
esp_coex headers to be unavailable when building minimal examples on
targets with both WiFi and IEEE802154 (e.g. esp32c5, esp32c6).
Moving init_coexist to esp_coex removes the cross-component dependency
and ensures the init function is only compiled when esp_coex itself is
part of the build. A linker hook is added to guarantee the object file
is not silently discarded by the linker.
Made-with: Cursor
- Introduced new HAL components for LCD and MIPI DSI, including:
- `lcd_hal.c` and `lcd_hal.h` for LCD hardware abstraction layer.
- `mipi_dsi_hal.c` and `mipi_dsi_hal.h` for MIPI DSI hardware
abstraction layer.
- Peripheral connection definitions in `lcd_periph.c` and
`lcd_periph.h`.
- Added necessary types and utility functions in `lcd_types.h` and
`mipi_dsi_types.h`.
- Updated CMakeLists to include the new HAL components in the build
system.
- Removed legacy references to LCD and MIPI DSI in the HAL and SOC
CMakeLists.
esp_stdio contains everything the old esp_vfs_console contained (the vfs stdio glue layer)
as well as other functionality related to stdio (previously referred to as console)
- Remove GPTIMER and TIMG related definitions from soc_caps_full.h files
- Move timer peripheral definitions to appropriate HAL layer files
- Update references across components to use proper HAL abstractions
- Consolidate timer group and GPTIMER capabilities organization
- Ensure consistent timer configuration across all ESP32 variants
This refactoring improves the separation of concerns between SOC
capabilities and HAL implementations for timer-related functionality.
This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
During cpu_start stack-smashing would errorounsly trigger when compiled
with -Os on P4. This happened due to the stack canary value (stored in bss) changing when
we initialized bss and then getting flagged as a stackoverflow.
Disable fstack-protector for cpu_start to avoid this issue
Similar to how the secondary init functions were already registered
via ESP_SYSTEM_INIT_FN, do the same for the core init functions.
This MR doesn't actually move the init functions into respective
components yet. This has to be carefully done in follow-up MRs.
Common spi functionality for sharing the SPI bus between modules is moved from esp_driver_spi to
a more fitting location in esp_hw_support (shared HW resource control).
This also allows us to decouple the spi_flash driver from esp_driver_spi, removing
esp_driver_spi and esp_ringbuf from G1 builds.
esp-system and esp-hw-support, and the rest of the g1 components, now only depend on
esp_driver_spi and esp_driver_gpio. Removing the rest of the driver components from g1 builds.
- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
Alexey Lapshin
Marius Vikhammer
Song Ruo Jing
Mahavir Jain
morris
Laukik Hase
Xiao Xufeng
Chen Chen
laokaiyao
armando
Chen Jichang
Alexey Gerenkov
Erhan Kurubas
C.S.M
Omar Chebib
Konstantin Kondrashov
Ivan Grokhotkov