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19 Commits
Author SHA1 Message Date
morris 4704a99af3 refactor(sdm): move sleep retention config into driver layer 
Move SDM regdma retention descriptors out of esp_hal_gpio and into
per-target
esp_driver_sdm sources so the driver owns its backup scope and restore
flow.
 2026-07-06 15:09:37 +08:00
morris 38c4f27102 fix(iomux): move clock source gating to IOMUX consumers 
Remove io_mux_set_clock_source internal source enabling and make SDM,
ana_cmpr, and gpio glitch filter drivers explicitly manage clock source
enable/disable with safe cleanup paths.
 2026-05-22 19:10:08 +08:00
wuzhenghui b7ec505923 feat(esp_driver_gpio): support rtc_io edge wakeup deepsleep 2026-05-20 11:04:00 +08:00
wuzhenghui c67d98fb10 change(soc): move _RTC_GPIO_EDGE_WAKEUP_SUPPORTED to soc_caps.h 2026-05-13 10:51:24 +08:00
Song Ruo Jing e689feee9d refactor(rtcio): align LP GPIO matrix related APIs with GPIO matrix APIs 2026-04-29 12:17:37 +08:00
Song Ruo Jing 1d50587ab2 refactor(rtcio): split rtcio/gpio switch with rtc iomux func sel func 
This allows rtc_gpio_deinit to always switch the pad back to GPIO,
regardless of lp io clock enabled or not, so that gpio_config can
always switch the IO back to GPIO use after wakeup from deep sleep.
 2026-04-29 12:17:37 +08:00
Song Ruo Jing 9c2a8281c1 fix(uart): lp uart rx iomux pin was not working as expected 
Introduced in 8818157e42
The workaround in the commit routes the signal to LP GPIO matrix first.
When uses LP IOMUX pin as UART RX, the signal did not bypass the matrix,
which caused the issue.

This commit adds rtc_gpio_iomux_input and rtc_gpio_iomux_output APIs
to align with existing GPIO driver APIs.
 2026-04-09 17:07:01 +08:00
morris e69f2c8346 refactor(gpio): derive SDM registers from GPIO_EXT 
Use GPIO_EXT.sigma_delta as the SDM register base on GPIO_EXT-based targets and remove standalone SDM symbols to eliminate manual offset/address maintenance risks.
 2026-04-08 15:07:27 +08:00
morris 572e732aca refactor(gpio): derive ETM registers from GPIO_EXT 
Use GPIO_EXT.etm as the ETM register base and remove standalone GPIO_ETM symbols to avoid manual offset address maintenance errors across targets.
 2026-04-08 15:07:27 +08:00
morris b79cf6d8eb feat(gpio): support glitch filter on esp32s31 2026-04-08 15:07:27 +08:00
Chen Chen cbb529bf97 feat(rtcio): support rtcio on esp32s31 2026-04-01 08:51:47 +08:00
Song Ruo Jing d4005779e0 fix(uart): improve uart rx glitch filter test case failing rate 
Not all IO glitch simulation functions were in iram before,
making the glitch too long to be filtered.
 2026-03-03 16:19:15 +08:00
Song Ruo Jing acb49e9520 fix(rtcio): RTC GPIO configuration should be written if LP IO clock exists 2026-03-02 15:03:30 +08:00
Song Ruo Jing 476004e4b8 fix(gpio): add esp_gpio_reserve check to gpio_config 2026-02-26 16:26:58 +08:00
armando bb6ea458d2 change(gpio): move gpio_num.h to gpio hal 2026-02-02 09:47:54 +08:00
morris ab4200e6f6 feat(twai): graduate the hal drivers into esp_hal_twai component 2025-12-01 22:32:54 +08:00
morris 580d9bca57 Merge branch 'refactor/esp_hal_gpio' into 'master' 
refactor(gpio): split GPIO HAL into separate component

Closes IDF-14089

See merge request espressif/esp-idf!43215
 2025-12-01 10:40:07 +08:00
Song Ruo Jing 06970a5284 refactor(esp_hal_gpio): move some caps definitions to esp_hal_gpio 2025-11-26 15:35:27 +08:00
Song Ruo Jing 1862fdec74 refactor(gpio): split GPIO HAL into separate component 
cleaned up some includes in GPIO peripheral files
 2025-11-26 15:35:07 +08:00