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3371 Commits

Author SHA1 Message Date
Jiang Jiang Jian
d27b57156f Merge branch 'feat/pm_components_ram_optimize_v6.0' into 'release/v6.0' 
feat(pm): pm components ram optimize (v6.0)

See merge request espressif/esp-idf!52426
 2026-09-15 12:03:15 +08:00
Laukik Hase
ab5b29e52c Merge branch 'fix/tee_reentrant_svc_and_non_det_sign_v6.0' into 'release/v6.0' 
feat(esp_tee): Backports to v6.0

See merge request espressif/esp-idf!52290
 2026-09-07 10:10:44 +05:30
morris
c2638a5689 Merge branch 'fix/i2s_tdm_5slot_clock_test_v6.0' into 'release/v6.0' 
fix(hal): prevent overflow in fractional clock division (v6.0)

See merge request espressif/esp-idf!51430
 2026-09-04 17:56:03 +08:00
wuzhenghui
38493ef42a change(esp_hw_support): optimize pmu_sleep RAM cost 2026-09-04 14:51:01 +08:00
Laukik Hase
eb0a81b89a feat(hal): Add LL-API to check whether RNG is enabled 
- Also add RNG LL-APIs for ESP32-C61
 2026-09-04 10:23:24 +05:30
Fu Hanxi
ddb9fd017c ci: apply idf-ci 1.x 2026-09-03 20:24:50 +02:00
Chen Chen
a207ed52f9 fix(hal): prevent overflow in fractional clock division 
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-08-20 14:46:58 +08:00
Pranav Sonawane
18f69206f3 change(hal): exclude PSRAM anti-FI check from bootloader and TEE builds 
The PSRAM encryption anti-FI check in mmu_ll_write_entry() pulls in
  ESP_FAULT_ASSERT and efuse_hal_chip_revision(), which inflate the
  bootloader image size. The check is not meaningful in the bootloader
  or in the ESP-TEE build, so guard it out for both.

  Applies to esp32c5, esp32c61 and esp32p4.
 2026-08-07 10:30:13 +05:30
Mahavir Jain
c9fc9d6103 Merge branch 'fix/esp_image_format_v6.0' into 'release/v6.0' 
fix(esp_image_format): Fix some memory-safety issues (v6.0)

See merge request espressif/esp-idf!50180
 2026-07-24 17:16:22 +05:30
Konstantin Kondrashov
decd12a726 fix(esp_image_format): validate MMU page size 2026-07-21 13:35:35 +03:00
Ashish Sharma
dc44ca9a86 fix(esp_tee): enforce MMU-map vaddr validity at the REE->TEE boundary 2026-07-17 18:15:36 +05:30
Scramble Tools
e0becb9e43 fix(esp_eth): use stored base_increment when computing PTP addend 
The addend in `emac_hal_ptp_start()` was derived from the floating-point
`config->ptp_req_accuracy_ns` instead of the integer `base_increment`
register that actually drives the sub-second update. The cast to
`uint8_t` loses the fractional part, so the un-corrected addend leaves
the PTP clock running off-rate.

Example: with a 40 MHz XTAL and the default `req_accuracy_ns = 40`,
`base_increment` rounds 85.899 up to 86, leaving the clock +1170 ppm
fast — well outside the IEEE 802.1AS neighborRateRatio limit (~±200
ppm), so strict-1AS bridges refuse asCapable.

Compute the addend from the stored `base_increment` for both rollover
modes: `addend = 2^32 * clk_period_ns / increment_ns`.

Measured on ESP32-P4: neighborRateRatio drops from +1147.5 ppm to
+4.2 ppm, and asCapable is granted.

Co-authored-by: Ondrej Kosta <panzer412@gmail.com>
 2026-07-07 08:37:04 +02:00
Jiang Jiang Jian
af3cf03943 Merge branch 'bugfix/esp_idf_ulp_wakeupcauses_record_v6.0' into 'release/v6.0' 
fix(ulp): record wakeup causes before lp core request sleep v6.0

See merge request espressif/esp-idf!49142
 2026-06-30 16:48:50 +08:00
hebinglin
a764b5f222 fix(ulp): record wakeup causes before lp core request sleep 2026-06-29 16:25:56 +08:00
Mahavir Jain
e7cd4a1500 feat(esp_psram): add option to carve unencrypted PSRAM region 
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
 2026-05-21 20:54:30 +05:30
Mahavir Jain
36f3329a23 Merge branch 'feature/recovery_bootloader_support_v6.0' into 'release/v6.0' 
feat(bootloader): Support recovery bootloader for ESP32P4 (v6.0)

See merge request espressif/esp-idf!48468
 2026-05-15 09:52:49 +05:30
Konstantin Kondrashov
9e03819d91 feat(efuse): Update efuse table for ESP32-H4 2026-05-14 14:42:49 +08:00
Konstantin Kondrashov
a742bd519a feat(bootloader): Support recovery bootloader for ESP32P4/C61 2026-05-13 10:18:15 +03:00
Alexey Lapshin
85bb42da29 fix(libc): picolibc: workaround wrong pthread_exit declaration for c++ 2026-04-29 18:36:02 +07:00
Konstantin Kondrashov
e34be7afd5 feat(hal): Adds half-word read/write checks for efuse 2026-03-25 10:31:10 +08:00
morris
7828edd986 Merge branch 'refactor/split_bod_hal_v6.0' into 'release/v6.0' 
refactor(bod): Move bod hal to pmu hal component (backport v6.0)

See merge request espressif/esp-idf!46411
 2026-03-23 11:02:07 +08:00
Jiang Jiang Jian
81daeadf9f Merge branch 'esp32h4_debug_asistant_v6.0' into 'release/v6.0' 
feat(esp32h4): add assist_debug/bus_monitor support (v6.0)

See merge request espressif/esp-idf!45949
 2026-03-23 10:38:51 +08:00
C.S.M
39ea6efc7c refactor(bod): Move bod hal to pmu hal component 2026-03-20 15:09:38 +08:00
Marius Vikhammer
613f8eaaed Merge branch 'feat/esp_hal_sdmmc_v6.0' into 'release/v6.0' 
sd: esp_hal_sd component (v6.0)

See merge request espressif/esp-idf!45623
 2026-03-20 10:04:21 +08:00
Erhan Kurubas
4a7d67df84 feat(esp32h4): add assist_debug stack monitoring support 2026-03-19 11:40:44 +08:00
Erhan Kurubas
18a583e517 refactor(hal): update assist_debug_ll_reset_register() to pass core_id 2026-03-19 11:40:44 +08:00
armando
45ec3b962b fix(spm): rename scp (scratchpad) to spm (scratchpad memory) 2026-03-18 09:49:59 +08:00
armando
1b85ad5081 change(mem): deprecated tcm and added scp memory utils 2026-03-18 09:49:59 +08:00
armando
fe5b8358f3 feat(hal):graudate the sdmmc/sdio_slave hal driver into a new component 2026-02-04 19:00:57 +08:00
Jiang Jiang Jian
25fad8e13f Merge branch 'feat/split_154_hal_components_v6.0' into 'release/v6.0' 
feat(ieee802154): separated the 802.15.4 HAL codes from the HAL component (v6.0)

See merge request espressif/esp-idf!44966
 2026-02-02 19:07:06 +08:00
morris
f3c93ba7d4 Merge branch 'refactor/cleanup_hal_files_v6.0' into 'release/v6.0' 
refactor(jpeg): Split hal layer for jpeg  (backport v6.0)

See merge request espressif/esp-idf!45514
 2026-02-01 18:51:36 +08:00
Jiang Jiang Jian
afa266ebd6 Merge branch 'fix/fix_i2c_modem_clock_ref_count_mismatch_v6.0' into 'release/v6.0' 
feat(esp_hw_support): add reference count control & clock enable checking for modem clock devices (v6.0)

See merge request espressif/esp-idf!45533
 2026-02-01 11:54:27 +08:00
C.S.M
e794bd6c5c refactor(hal): Cleanup some missing hal files 2026-02-01 10:15:18 +08:00
C.S.M
a3ca5b610d refactor(jpeg): Split hal layer for jpeg 2026-02-01 10:15:18 +08:00
Song Ruo Jing
89da3742b8 refactor(clk): split clock HAL into separate component 2026-01-31 22:32:37 +08:00
wuzhenghui
12b9fb6549 feat(esp_hal_rtc_timer): introduce new RTC timer component and refactor existing timer functions 2026-01-31 22:29:20 +08:00
Aditya Patwardhan
85e70bc138 fix(hal): Add brownout_hal for TEE builds 2026-01-30 17:12:55 +05:30
Aditya Patwardhan
6c2716cd27 refactor(hal): Created esp_hal_security for security code 2026-01-30 17:12:49 +05:30
morris
aa4034b197 Merge branch 'feature/graduate_tsens_hal_component_v6.0' into 'release/v6.0' 
feat(tsens): graduate temperature sensor hal component (v6.0)

See merge request espressif/esp-idf!44357
 2026-01-30 18:43:06 +08:00
wuzhenghui
8e67e95815 feat(esp_hw_support): implement CHECK_ENABLE operations for modem clock control functions 2026-01-30 15:30:34 +08:00
zwx
eed0b0e5ae feat(ieee802154): separated the 802.15.4 HAL codes from the HAL component 2026-01-30 06:15:26 +00:00
morris
799e366cee Merge branch 'feat/esp_driver_dma_v6.0' into 'release/v6.0' 
feat(dma): graduate the dma driver from esp_hw_support to esp_driver_dma (v6.0)

See merge request espressif/esp-idf!45387
 2026-01-30 12:40:39 +08:00
Aditya Patwardhan
f6fbbd94df Merge branch 'feat/enable_ecdsa_support_for_esp32p4_eco5_v6.0' into 'release/v6.0' 
feat(esp32p4_eco5): enabled ECDSA peripheral support for ESP32P4 ECO5 (v6.0)

See merge request espressif/esp-idf!45350
 2026-01-30 07:47:55 +05:30
morris
db750dc1a0 feat(dma): graduate the dma driver from esp_hw_support to esp_driver_dma 2026-01-29 14:41:14 +08:00
Jiang Jiang Jian
b28d6715ee Merge branch 'feat/esp32p4_eco5_emac_v6.0' into 'release/v6.0' 
Added PTP PPS Feature (v6.0)

See merge request espressif/esp-idf!45060
 2026-01-29 14:01:33 +08:00
nilesh.kale
2ab4d5cf48 feat: enabled ECDSA peripheral support for ESSP32-P4 2026-01-29 11:24:47 +05:30
nilesh.kale
1ec1612cb5 fix(hal/test_apps): moved key manager tests under flash encryption check 
These two tests executed when FPGA setup is there and pass only when
flash encryption is switched on. So, this tests been moved under FE check.
 2026-01-29 11:15:33 +05:30
laokaiyao
2cb958a9e3 feat(tsens): graduate temperature sensor hal component 2026-01-29 10:05:47 +08:00
morris
7c1e88e3d4 Merge branch 'refactor/cam_fourcc_v6.0' into 'release/v6.0' 
refactor(cam): use fourcc for cam format (v6.0)

See merge request espressif/esp-idf!45421
 2026-01-28 22:39:09 +08:00
morris
39dc9613c1 Merge branch 'refactor/remove_gdma_trigger_peripheral_t_v6.0' into 'release/v6.0' 
refactor: remove gdma_trigger_peripheral_t (v6.0)

See merge request espressif/esp-idf!45063
 2026-01-28 22:37:24 +08:00