`i2c_master_isr_handler_default()` may set HPTaskAwoken to pdTRUE via
`xQueueSendFromISR()` (event_queue), `xSemaphoreTakeFromISR()` and
`xSemaphoreGiveFromISR()` on `bus_lock_mux`. When the device list lookup
returns no matching device, the function returned directly, skipping
the `portYIELD_FROM_ISR()` at the bottom of the handler. A higher-
priority task waiting on the bus mux or the event queue would then have
to wait for the next scheduler tick instead of being preempted into
immediately, inflating worst-case event latency.
Replace the early return with a goto to the existing yield check at the
end of the ISR.
Merges https://github.com/espressif/esp-idf/pull/18569
fix(nimble): Always read initial BAS level and forward HID report/control/protocol writes as HIDD events (v5.5)
See merge request espressif/esp-idf!48693
Introduced in 8818157e42
The workaround in the commit routes the signal to LP GPIO matrix first.
When uses LP IOMUX pin as UART RX, the signal did not bypass the matrix,
which caused the issue.
This commit adds rtc_gpio_iomux_input and rtc_gpio_iomux_output APIs
to align with existing GPIO driver APIs.
This allows rtc_gpio_deinit to always switch the pad back to GPIO,
regardless of lp io clock enabled or not, so that gpio_config can
always switch the IO back to GPIO use after wakeup from deep sleep.
Verify prop_seg is correctly included in the programmed TSEG1 hardware
register when using the legacy twai_driver_install() with prop_seg > 0.
Closes https://github.com/espressif/esp-idf/issues/18477
PMP entry 3 (SOC_DROM_MASK_HIGH, TOR mode) in the memprot path
was incorrectly granted RW permission on esp32h21 and esp32c61.
The mask ROM data region is inherently read-only; remove the W bit.
Also added necessary tests to check voilations and re-enabled
tests for ESP32P4
sec1_new_session()/sec2_new_session() were calling sec*_close_session()
with the *new* session_id parameter instead of the existing
cur_session->id. The close handler validates `cur_session->id ==
session_id` before performing teardown, so the call always failed with
ESP_ERR_INVALID_STATE.
Effect: when a peer started a new provisioning session while another was
already active, the previous session's PSA keys, AES context, SRP handle
and username buffer were leaked instead of being destroyed. The cleared
session struct was overwritten by the new session, leaking the previous
key handles inside PSA Crypto and (for security2) leaking heap memory
for the username and SRP context.
Fix: pass cur_session->id so the close path actually executes the
teardown (psa_destroy_key/psa_cipher_abort/esp_srp_free/free) before the
new session takes over.
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.
The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.
This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
Martin Vychodil
DatanoiseTV
Euripedes Rocha
Jiang Jiang Jian
Rahul Tank
Song Ruo Jing
wanckl
Michael.B
diplfranzhoepfinger
wanglei
Chen Chen
Wang Meng Yang
sonika.rathi
surengab
linruihao
hebinglin
Mayank Tyagi
nilesh.kale
Mahavir Jain
Kapil Gupta
sibeibei
Aditya Patwardhan
muhaidong