Commit Graph
14 Commits
Author SHA1 Message Date
wuzhenghui d3c628c759 change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT caps 2026-07-09 17:31:43 +08:00
Mahavir Jain 77e85b886a docs(esp_psram): clarify carve-out location is at upper end of PSRAM
The previous wording "top of PSRAM" was ambiguous: the carve-out is
actually mapped at the highest physical addresses of PSRAM (after the
rodata, text, and main heap mappings). Update the Kconfig help text for
SPIRAM_ENC_EXEMPT and SPIRAM_ENC_EXEMPT_SIZE, the External RAM
documentation, and the internal layout comment to say "upper end of PSRAM
(highest physical addresses)" instead.
2026-05-21 20:54:31 +05:30
Mahavir Jain 10d2d9cb9f docs(esp_psram): document MALLOC_CAP_SPIRAM_NO_ENC carve-out
Extends the External RAM encryption section to describe
CONFIG_SPIRAM_ENC_EXEMPT and the MALLOC_CAP_SPIRAM_NO_ENC heap
capability, including a security warning and a typical DMA-alignment
use case. Mirrors the change in zh_CN.
2026-05-21 20:54:30 +05:30
Mahavir Jain e7cd4a1500 feat(esp_psram): add option to carve unencrypted PSRAM region
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
2026-05-21 20:54:30 +05:30
Marius Vikhammer d09e551417 docs: clarify PSRAM default allocation behavior
Clarify that MALLOC_CAP_DEFAULT describes a memory capability
rather than the malloc() placement policy, so PSRAM-backed
capability allocations are documented correctly when malloc()
remains internal-only by default.

Closes https://github.com/espressif/esp-idf/issues/18391

Made-with: Cursor
2026-03-27 10:05:28 +08:00
Mahavir Jain 2b82146902 fix(esp_psram): make SPIRAM_USE_MEMMAP available for all targets
This reverts earlier commit d2858847 and thereby making SPIRAM_USE_MEMMAP
available for all targets.

This config option has no direct usage but just avoids adding the PSRAM
to heap but still keeps it memory mapped.

Closes https://github.com/espressif/esp-idf/issues/17764
2025-11-05 14:07:09 +05:30
Mahavir Jain d2858847b2 fix(esp_psram): make SPIRAM_USE_MEMMAP depend on ESP32 target 2025-08-11 18:06:11 +05:30
harshal.patil ab229a34b3 feat(cpu_region_protect): Enable basic memory protection for SPIRAM 2025-04-29 11:48:27 +05:30
harshal.patil 46225a4026 feat(esp_psram): Add a new API to just detect and enable the PSRAM
- esp_psram_chip_init() just detects and does basic initialisations of PSRAM
- esp_psram_init() initialises and maps/loads the PSRAM pages
2025-04-29 11:48:27 +05:30
wangtao@espressif.com e65acc9510 feat(wifi): fix SPIRAM_IGNORE_NOTFOUND releated config 2024-10-24 19:49:57 +08:00
Chen Jichang 1c1f536235 feat(psram): add psram noinit segment support on S2/S3/P4/C5
Closes https://github.com/espressif/esp-idf/issues/14253
2024-08-21 12:13:16 +08:00
muhaidong f37448cddb fix(wifi): fix psram enabled but initialized fail issue
Closes https://github.com/espressif/esp-idf/issues/11971
2023-12-05 11:19:59 +08:00
Armando 712c0c0075 feat(psram): esp32p4 psram device driver support 2023-08-28 14:14:58 +08:00
Armando 38e5043ae8 esp_psram: new psram component 2022-06-14 15:44:27 +08:00