Commit Graph
148 Commits
Author SHA1 Message Date
wuzhenghui c17787722c docs(esp_system): add detailed RTC memory layout documentation 2026-01-09 11:15:15 +08:00
wuzhenghui 9a20ef85f5 fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21 2026-01-09 11:15:12 +08:00
Li Shuai 0335029a7b fix(ld): fix cannot move location counter backwards (from 3fc88000 to 3fc87fff) 2026-01-04 10:44:33 +08:00
Marius Vikhammer da1829ed25 fix(system): removed the exe flag from psram memory for esp32
extern_ram_seg segment was marked as RWX in the linker script
even though we cannot run code from PSRAM on ESP32.

This is a link-time check, and actual CPU RWX permissions are
controlled seperately so this has no practical implications,
but it could mistakenly be remarked upon during security scans
or checks by customers.
2025-12-29 16:39:01 +08:00
Alexey Lapshin ad7f4b9670 feat(esp_libc): make picolibc default libc 2025-12-06 00:08:35 +07:00
Marius Vikhammer 72c7bfe2e2 fix(system): fixed constructors not working properly on P4 ECO5 2025-11-25 13:35:51 +05:30
Marius Vikhammer 02b891f9de fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP 2025-11-25 13:35:50 +05:30
armando 714b022a43 ci(p4): disable p4 rev3 invalid tests temporarily 2025-11-21 02:48:05 +00:00
Laukik Hase 2cb0fa5c34 feat(esp_tee): Support for ESP32-C61 - the rest of the components 2025-11-19 10:57:42 +05:30
wuzhenghui 5eff18eec2 fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep 2025-11-11 21:58:51 +08:00
Alexey Lapshin d9389ba082 change(bootloader): rename bootloader.ld -> bootloader.ld.in
This change passes file through compiler preprocessor which unlocks
future code refactoring.
2025-09-24 00:51:54 +08:00
Konstantin Kondrashov 8e7ed24eb6 feat(log): Reserve first 4 bytes as zero for vars pointed to NULL
For bin log, reserve the first 4 bytes as zero for variables that are pointed to NULL
and should not be printed in the log. So the esp-idf-monitor will skip printing
those variables.
2025-09-15 15:40:45 +03:00
armando 179d00a6f8 feat(p4): p4 rev3 real chip support 2025-08-28 17:56:16 +08:00
Laukik Hase 340de9823a feat(esp_tee): Support for ESP32-C5 - the rest of the components 2025-08-13 14:08:59 +05:30
Alexey Lapshin 019dc93ae0 feat(esp_system): switch to standard __libc_init_array initialization
Initially, ESP-IDF used the do_global_ctors() function to run global
constructors. This was done to accommodate Xtensa targets that emit
.ctors.* sections, which are ordered in descending order.

For RISC-V, compilation used .init_array.* sections, which are designed
to have ascending order. Priority constructors in .init_array.* sections
were correctly processed in ascending order. However, non-priority
.init_array section was processed in descending order, as it was done
for Xtensa .ctors.

Starting with ESP-IDF v6.0, the implementation switched to the standard
LibC behavior (__libc_init_array()), which processes both priority and
non-priority constructors in ascending order.

To achieve this, a breaking changes were introduced:
  - Xtensa .ctors.* priority entries converted to .init_array.* format
    (ascending), to be passed to __libc_init_array().
  - Processing order of non-priority .init_array and .ctors sections was
    changed from descending to ascending.

Also, this change introduces .preinit_array for linking. This may be
needed for some C++ or sanitizer features.

Related to https://github.com/espressif/esp-idf/issues/15529
2025-08-04 11:33:44 +08:00
armando 9be8dccef5 feat(psram): psram support on h4 2025-07-28 10:16:48 +08:00
armando bcf04e356b resolve comments, to squash 2025-07-10 06:24:32 +00:00
armando dfb0662de2 feat(esp32p4): support eco5 on fpga 2025-07-10 06:24:32 +00:00
Laukik Hase 12e2df2d74 feat(esp_tee): Support for ESP32-H2 - the rest of the components 2025-05-20 16:31:23 +05:30
Omar Chebib 6918a45ee6 fix(esp_system): fix RTC reserved area alignment in the linker script
Make sure the size of the RTC reserved area complies with the alignment requirement.

Closes https://github.com/espressif/esp-idf/issues/13082
2025-05-15 16:11:19 +08:00
harshal.patil 3123fff18a fix(esp_psram): Add XIP PSRAM alignment gaps in heap only if PSRAM protection is enabled 2025-05-05 10:50:19 +05:30
Harshal Patil d898c2398b Merge branch 'feat/some_xip_psram_related_optimisations_and_fixes' into 'master'
feat(esp_psram): Fix late PSRAM init and add some wasted XIP PSRAM memory in heap

Closes IDF-11463 and IDF-10555

See merge request espressif/esp-idf!37116
2025-04-30 00:02:19 +08:00
harshal.patil ab229a34b3 feat(cpu_region_protect): Enable basic memory protection for SPIRAM 2025-04-29 11:48:27 +05:30
Marius Vikhammer 1256078ea2 feat(esp32h21): added support for misc core system features 2025-04-28 11:42:25 +08:00
Konstantin Kondrashov 204046e799 feat(log): Add binary logging support 2025-04-23 15:46:34 +08:00
laokaiyao 0abc755342 feat(rom): update rom for c5 eco2
Breaking: Starting from this commit, ESP-IDF can only support ESP32-C5 v1.0 (ECO2)
2025-04-16 11:01:36 +08:00
Chen Jichang 8670800827 refactor(esp32h4): refactor memory.ld and section.ld 2025-03-11 16:48:21 +08:00
Chen Jichang 8e8c0573b4 feat(esp32h4): support esp_system, esp_timer and freertos (stage6) 2025-03-11 16:48:21 +08:00
Chen Jichang 6f83f39dce feat(esp32h4): introduce target esp32h4(stage 1) 2025-02-08 17:07:44 +08:00
Omar Chebib 414c7056a2 fix(esp_system): add missing aaray attribute in the ESP32-P4 linker script 2024-12-30 18:36:58 +08:00
gaoxu b240defc75 feat(esp32h21): support esp_system, esp_timer and freertos (stage5) 2024-12-20 22:43:10 +08:00
Alexey Lapshin bcd80c92f3 Merge branch 'fix/reduce_rtc_text_size' into 'master'
fix(system): linker script: free unused .rtc.text memory for esp32c3, esp32s2

See merge request espressif/esp-idf!33972
2024-12-03 13:22:45 +08:00
Alexey Lapshin 244c369cd8 fix(xtensa): fix confusing backtrace when PC is invalid
Before this change _invalid_pc_placeholder pointed to address of _init
function from crti.o
This made GDB input a bit confusing:

  0x40080400 in _init ()
  (gdb) bt
  #0  0x40080400 in _init ()
  #1  0x400e519a in test_instr_fetch_prohibited () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_panic.c:271
  #2  0x400d89a7 in app_main () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_app_main.c:116
  #3  0x400e5f22 in main_task (args=0x0) at /home/alex/git/esp-idf/components/freertos/app_startup.c:208
  #4  0x400895a8 in vPortTaskWrapper (pxCode=0x400e5eb0 <main_task>, pvParameters=0x0) at /home/alex/git/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:139

After the change GDB prints output that contains a hint:

  _invalid_pc_placeholder () at /home/alex/git/esp-idf/components/xtensa/xtensa_vectors.S:2235
  2235	    UNREACHABLE_INSTRUCTION_CHECK_PREVIOUS_FRAMES
  (gdb) bt
  #0  _invalid_pc_placeholder () at /home/alex/git/esp-idf/components/xtensa/xtensa_vectors.S:2235
  #1  0x400e519e in test_instr_fetch_prohibited () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_panic.c:271
  #2  0x400d89ab in app_main () at /home/alex/git/esp-idf/tools/test_apps/system/panic/main/test_app_main.c:116
  #3  0x400e5f26 in main_task (args=0x0) at /home/alex/git/esp-idf/components/freertos/app_startup.c:208
  #4  0x400895a8 in vPortTaskWrapper (pxCode=0x400e5eb4 <main_task>, pvParameters=0x0) at /home/alex/git/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:139
2024-12-02 21:36:00 +07:00
Alexey Lapshin 8454aefc25 fix(esp_system): avoid placing sections between ASSERT_SECTIONS_GAP checks 2024-12-02 20:26:26 +07:00
Alexey Lapshin d0f05cd690 fix(esp_system): fix binary generation error when no eh_frame but TLS
ERROR:
A fatal error occurred: Segment loaded at 0x3c01d150 lands in same 64KB flash
mapping as segment loaded at 0x3c018020. Can't generate binary. Suggest
changing linker script or ELF to merge sections.

Seems binary generator does not handle well empty sections that contains
aligning only. I did not investigate much but this change helped.
2024-12-02 20:26:26 +07:00
Laukik Hase 733741bbac feat(esp_tee): Support for ESP-TEE - esp_system component 2024-12-02 12:20:04 +05:30
Alexey Lapshin 3c5d24e607 fix(system): linker script: free unused .rtc.text memory for esp32c3/esp32s2/esp32s3 2024-11-19 19:46:15 +08:00
gaoxu 64bbb53b8f feat(esp32h21): introduce target esp32h21(stage 1) 2024-11-12 15:42:27 +08:00
Erhan Kurubas f4eec4da48 feat(esp_system): preload openocd stub binaries and reserve memory for debugging 2024-09-26 20:16:04 +02:00
Chen Jichang 309e4d09bd fix(psram): fix macro in memory.ld 2024-09-19 13:46:57 +08:00
Alexey Lapshin c605620073 Merge branch 'fix/keep-got-sections-for-riscv' into 'master'
feat(esp_system): drop .got* sections and add hint

See merge request espressif/esp-idf!32969
2024-09-06 19:21:06 +08:00
Alexey Lapshin 73987108cd feat(esp_system): drop .got* sections and add hint
Closes https://github.com/espressif/esp-idf/issues/14296
2024-09-05 15:47:01 +07:00
Marius Vikhammer 520fda61cd feat(system): remove references to RTC mem on C61 2024-09-04 11:16:36 +08:00
harshal.patil 95f286555a fix(esp_hw_support): Use _iram_text_end instead of _iram_end for I/D-RAM split 2024-08-28 11:16:27 +05:30
Marius Vikhammer c91d481dc9 feat(ulp): remove ulp related C61 code 2024-08-27 17:23:19 +08:00
C.S.M 271ca9f85a feat(spiram): Add .noinit and .bss segement support on esp32c61 2024-08-22 10:58:50 +08:00
Chen Jichang 1c1f536235 feat(psram): add psram noinit segment support on S2/S3/P4/C5
Closes https://github.com/espressif/esp-idf/issues/14253
2024-08-21 12:13:16 +08:00
Erhan Kurubas 9b38f87781 Revert "Merge branch 'add_openocd_stub_bins' into 'master'"
This reverts merge request !31504
2024-08-09 22:49:43 +02:00
Erhan Kurubas c7931b0782 feat(esp_system): preload openocd stub binaries and reserve memory for debugging 2024-08-08 23:25:26 +02:00
Armando 23fcfcae8b change(cache): added cache size kconfig macro on s2 2024-07-25 14:25:19 +08:00