9 Commits

Include renames

Author	SHA1	Message	Date
cjin	5307ec1f92	feat(ble): add config for reserved controller memory on ESP32C5	2026-02-04 00:07:44 +08:00
zhaoweiliang	1fc9676c99	feat(ble): support adv fast tx feature on ESP32-C5	2026-02-04 00:07:44 +08:00
cjin	debd743a0b	feat(ble): support sid filter feature on ESP32C5	2026-01-16 12:51:55 +05:30
cjin	6c15fccddd	feat(ble): support pawr feature in ble sdk on ESP32-C5	2025-08-18 19:18:10 +08:00
zwl	6f0a61ab0d	fix(ble): fixed dtm function error on ESP32-C5	2025-07-31 14:53:29 +08:00
cjin	afee51e0ef	feat(ble): enable broker initialization on ESP32-C5	2025-07-09 11:25:23 +08:00
cjin	a5c32a5fb7	feat(ble): support configurable rxbuf opt feat on ESP32-C5	2025-04-16 14:36:48 +08:00
Shen Weilong	11289ffe86	feat(ble/controller): Added memory boundary check for ESP32-C5	2025-03-25 15:08:52 +08:00
Shen Weilong	c2449607dc	change(ble): Supported cuttable architecture for ble	2025-02-19 12:07:16 +08:00