ESP32-S31 uses the same trace encoder IP as ESP32-P4. Of the E-Trace v2.0
parameters the two targets report, only privilege_width_p differs (1 on P4,
2 on S31), and it affects both the sync packet layout and the filter's
privilege selector.
- Add the SOC_RISCV_TRACE_* caps for ESP32-S31 along with the esp32s31 LL, and
declare TRACE0/TRACE1 in the target's trace_struct.h.
- Carry privilege_width_p as SOC_RISCV_TRACE_PRIV_WIDTH so the sync packet
decoder can locate the address field, which starts one bit later on targets
that implement supervisor mode.
- Use the RISC-V architectural privilege encoding (0 user, 1 supervisor,
3 machine) in the public filter enum so the values do not change per target,
and let each LL narrow them to its own register field.
- Add riscv_trace_ll_priv_is_supported() per target, so a privilege level the
selector cannot represent is rejected with ESP_ERR_NOT_SUPPORTED rather than
being silently narrowed to a different level. It lives next to the narrowing
code so the two cannot drift apart.
- Fix trace buffer allocation on targets whose internal RAM is not reached
through a cache. esp_cache_get_alignment() reports 0 there, which underflowed
the size check and failed every allocation. Align base and size to the larger
of the reported cache line and the encoder's 4-byte write granularity.
riscv_trace_ll_enable_bus_clock and riscv_trace_ll_reset_register operate
on shared HP_SYS_CLKRST registers and were called concurrently from both
cores during SECONDARY init, creating RMW race conditions.
Move the clock/reset logic out of the HAL layer into
esp_riscv_trace_early_init, protected by PERIPH_RCC_ATOMIC() spinlock.
Wrap the LL functions with macros that enforce the caller must be inside
a PERIPH_RCC_ATOMIC() critical section at compile time.
Erhan Kurubas
morris