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48,486 Commits 25 Branches 192 Tags
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3137 Commits
Author SHA1 Message Date
morris 16ceaa002b Merge branch 'bugfix/dma2d_dequeue_mechanism_v5.5' into 'release/v5.5' 
fix(dma2d): add a dequeue mechanism for dma2d driver (v5.5)

See merge request espressif/esp-idf!50515
 2026-07-18 15:55:39 +08:00
morris 26654f5a76 Merge branch 'bugfix/uart_sw_flow_ctrl_xoff_char_v5.5' into 'release/v5.5' 
fix(uart): fix uart sw flow ctrl XOFF char write to wrong reg on ESP32C6 (v5.5)

See merge request espressif/esp-idf!50525
 2026-07-18 15:54:51 +08:00
morris 502fb705a2 Merge branch 'fix/twai_ci_job_pollution_v5.5' into 'release/v5.5' 
fix(ci): twai test close board to fixed ci jobs pullotion (v5.5)

See merge request espressif/esp-idf!49921
 2026-07-18 15:51:55 +08:00
morris 15558ba694 Merge branch 'fix/twaifd_assert_fail_v5.5' into 'release/v5.5' 
fix(driver_twai): fix driver assert fail when send frame (v5.5)

See merge request espressif/esp-idf!49942
 2026-07-18 15:46:42 +08:00
Jiang Jiang Jian cc5a3fbcb5 Merge branch 'feat/psram_enc_exempt_v5.5' into 'release/v5.5' 
feat(esp_psram): add option to carve unencrypted PSRAM region (v5.5)

See merge request espressif/esp-idf!49931
 2026-07-16 17:04:28 +08:00
wanckl 436d44260f feat(driver_twai): fd hardware support time trigger trans 2026-07-15 11:51:34 +08:00
Song Ruo Jing d431d87261 fix(uart): fix uart sw flow ctrl XOFF char write to wrong reg on ESP32C6 
Add software flow control test case

Introduced in e6ef4d1791

Closes https://github.com/espressif/esp-idf/issues/18779
 2026-07-09 20:32:15 +08:00
Song Ruo Jing 632adbfa6f fix(dma2d): fix non-usable DMA2D_CSC_TX_SCRAMBLE option 2026-07-08 23:14:53 +08:00
wanckl 70b0edb30a feat(driver_twai): support using all 4 hardware tx buffer 2026-06-26 18:35:09 +08:00
wanckl f4cf285425 fix(driver_twai): fixed twaifd slow bitrate trans faile on correct bitrate 2026-06-26 18:35:09 +08:00
morrisandCursor 52e73f3cd5 fix(sdio_slave): align buffer size checks with descriptor limits 
Define per-target SDIO slave descriptor buffer limits in the LL layer and validate queued send buffers against the 4-byte aligned effective maximum. Update the public docs to describe the chip-dependent limit instead of hardcoding 4092 bytes.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-06-25 11:39:41 +08:00
Mahavir Jain 0044542811 feat(esp_psram): add option to carve unencrypted PSRAM region 
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
 2026-06-23 14:56:38 +05:30
Jiang Jiang Jian 9098c60919 Merge branch 'bugfix/fix_some_wifi_bugs_260617_v5.5' into 'release/v5.5' 
fix(wifi): fix some wifi bugs 260617 backport v5.5

See merge request espressif/esp-idf!49777
 2026-06-22 20:38:53 +08:00
morris 41fed73659 Merge branch 'change/update_c61_gdma_header_v5.5' into 'release/v5.5' 
change(ahb_dma): update c61 eco3 header files (v5.5)

See merge request espressif/esp-idf!49837
 2026-06-22 18:04:05 +08:00
Jiang Jiang Jian bfb6b4a2b2 Merge branch 'feature/psram_halfsleep_mode_support_v5.5' into 'release/v5.5' 
feat(psram): allow PSRAM to enter halfsleep mode during light sleep (v5.5)

See merge request espressif/esp-idf!49760
 2026-06-22 12:25:04 +08:00
Chen Jichang 1096a381a9 change(ahb_dma): update c61 eco3 header files 2026-06-22 11:15:25 +08:00
sibeibei d4166e94d8 fix(wifi): fix modem sleep flag clear failed 2026-06-18 18:09:56 +08:00
wuzhenghui ddddb4d25c feat(esp_psram): wakeup PSRAM by CE# force control instead of dummy write 2026-06-18 16:06:00 +08:00
Song Ruo Jing 6079c74f99 feat(psram): allow PSRAM to enter halfsleep mode during light sleep 2026-06-18 16:05:49 +08:00
morris 5d7894cd8c Merge branch 'fix/uart_is_enable_check_error_on_s3_v5.5' into 'release/v5.5' 
Fix ESP32-S3 uart2 is_enabled check error (v5.5)

See merge request espressif/esp-idf!49349
 2026-06-18 10:29:30 +08:00
Jiang Jiang Jian ad91c6ed0f Merge branch 'feat/support_usb_wakeup_v5.5' into 'release/v5.5' 
feat: support usb as wakeup source from light sleep (v5.5)

See merge request espressif/esp-idf!49511
 2026-06-17 19:50:18 +08:00
gaoxu c99a3d7b82 fix(uart): fix ESP32-S3 uart2 is_ enabled check error 
(Closes https://github.com/espressif/esp-idf/issues/18690)
 2026-06-17 18:07:47 +08:00
morris 1ee7120c88 Merge branch 'bugfix/ppa_blend_yuv_hang_v5.5' into 'release/v5.5' 
fix(ppa): fix hang if blend operation on a YUV format input background image (v5.5)

See merge request espressif/esp-idf!49736
 2026-06-17 15:03:41 +08:00
Jiang Jiang Jian 2ed7f48d3d Merge branch 'fix/ecdsa_ecc_hw_input_validation_v5.5' into 'release/v5.5' 
Validate ECDSA signature range and harden ECC memory power-down (v5.5)

See merge request espressif/esp-idf!49431
 2026-06-17 11:59:02 +08:00
Jiang Jiang Jian 587bbfb58d Merge branch 'fix/remove_nonexistent_crypto_registers_c61_v5.5' into 'release/v5.5' 
Remove non-existent crypto registers (ESP32-C61) (v5.5)

See merge request espressif/esp-idf!49451
 2026-06-17 11:58:43 +08:00
Song Ruo Jing e6b556fc6d fix(ppa): fix hang if blend operation on a YUV format input background image 
Closes https://github.com/espressif/esp-idf/issues/18687
 2026-06-16 19:32:56 +08:00
harshal.patil 1a36a6409b fix(secure_boot): range-check ECDSA r,s in bootloader before ROM verify 2026-06-12 16:54:33 +05:30
harshal.patil 9514a0fd2f fix(esp_common): Add esp_fault_internal.h for use by G0 components 
In release/v5.x, esp_fault.h resides in the esp_hw_support (G1)
component, so the G0 components (hal, esp_rom) must not depend on it.
Copy its contents to esp_common as esp_fault_internal.h, keep
esp_fault.h as a compatibility wrapper around it, and switch the hal
and esp_rom ECDSA/ECC code to the internal header.
 2026-06-12 16:54:33 +05:30
harshal.patil 8a934fa932 test(mbedtls): Add out-of-bounds test for the ECDSA hardware driver 2026-06-12 16:54:33 +05:30
harshal.patilandAshish Sharma 483c51b3c8 fix(mbedtls): validate ECDSA signature range and harden ECC memory power-down 
Co-Authored-By: Ashish Sharma <ashish.sharma@espressif.com>
 2026-06-12 16:54:33 +05:30
morris a4ea351ef1 Merge branch 'fix/adc_monitor_error_on_ch8_9_on_s3_v5.5' into 'release/v5.5' 
Fix ADC Continuous Monitor Callback Failure for ADC1 Channels 8/9 on ESP32-S3 (v5.5)

See merge request espressif/esp-idf!49506
 2026-06-12 10:25:20 +08:00
morris 3fed4b029e Merge branch 'fix/fix_rgb_gdma_link_switch_v5.5' into 'release/v5.5' 
fix(rgb_lcd): fix gdma link switch not take effect (v5.5)

See merge request espressif/esp-idf!49546
 2026-06-11 17:41:10 +08:00
morris e2face00fa Merge branch 'fix/fix_parlio_valid_delay_max_value_v5.5' into 'release/v5.5' 
fix(parlio): fix max valid delay value (v5.5)

See merge request espressif/esp-idf!49392
 2026-06-11 14:08:53 +08:00
Chen Jichang 090a719e89 fix(rgb_lcd): fix gdma link switch not take effect 2026-06-11 10:35:39 +08:00
JiangGuangMingandCursor 33f65d3ff2 feat(esp_hal_usb): add usb suspend wakeup status in ll layer 
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-06-11 09:05:40 +08:00
gaoxu f511ee6e53 fix(adc): fix ADC monitor channel 8/9 error 
(Closes https://github.com/espressif/esp-idf/issues/17768)
 2026-06-10 15:10:23 +08:00
Song Ruo Jing cec524c576 fix(spi_flash): gpspi flash clock could reach higher frequency 2026-06-09 22:08:32 +08:00
harshal.patil 673c861ac2 fix(soc): Remove non-existent crypto registers (ESP32-C61) 2026-06-09 18:18:13 +05:30
Chen Jichang 0cb56b975b fix(parlio): fix max valid delay value 2026-06-08 17:52:17 +08:00
Scramble ToolsandOndrej Kosta 9bf5b6eed5 fix(esp_eth): use stored base_increment when computing PTP addend 
The addend in `emac_hal_ptp_start()` was derived from the floating-point
`config->ptp_req_accuracy_ns` instead of the integer `base_increment`
register that actually drives the sub-second update. The cast to
`uint8_t` loses the fractional part, so the un-corrected addend leaves
the PTP clock running off-rate.

Example: with a 40 MHz XTAL and the default `req_accuracy_ns = 40`,
`base_increment` rounds 85.899 up to 86, leaving the clock +1170 ppm
fast — well outside the IEEE 802.1AS neighborRateRatio limit (~±200
ppm), so strict-1AS bridges refuse asCapable.

Compute the addend from the stored `base_increment` for both rollover
modes: `addend = 2^32 * clk_period_ns / increment_ns`.

Measured on ESP32-P4: neighborRateRatio drops from +1147.5 ppm to
+4.2 ppm, and asCapable is granted.

Co-authored-by: Ondrej Kosta <panzer412@gmail.com>
 2026-06-03 14:17:02 +02:00
morris 6a3dab1b4b Merge branch 'fix/fix_mipi_lcd_dirty_buffer_v5.5' into 'release/v5.5' 
feat(lcd): support buffer switch interrupt (v5.5)

See merge request espressif/esp-idf!49102
 2026-06-03 18:43:36 +08:00
Chen Jichang e1d48975fb feat(lcd): support buffer switch interrupt 2026-06-02 19:35:19 +08:00
hebinglin c0f21a426d fix(esp_hw_support): fix LP core exception interrupt not being cleared 2026-06-02 17:01:24 +08:00
hebinglin 4a42a8847b fix(ulp): record wakeup causes before lp core request sleep 2026-06-01 21:11:48 +08:00
Aditya Patwardhan 9234e95e20 Merge branch 'feat/generic_key_mgr_key_types_v5.5' into 'release/v5.5' 
Store key_len field in the key_config (v5.5)

See merge request espressif/esp-idf!48145
 2026-05-28 10:42:25 +05:30
morris dd244bf035 Merge branch 'idfgh-17542_v5.5' into 'release/v5.5' 
hal/twai: honor prop_seg in legacy timing config (v5.5)

See merge request espressif/esp-idf!48187
 2026-05-28 11:21:05 +08:00
morris 2c99af12a0 Merge branch 'bugfix/isp_gamma_xcoord_error_v5.5' into 'release/v5.5' 
fix(isp): disable gamma xcoord error check (v5.5)

See merge request espressif/esp-idf!48286
 2026-05-26 13:54:10 +08:00
morris 2e06562399 Merge branch 'bugfix/rtc_gpio_deinit_for_deep_slp_v5.5' into 'release/v5.5' 
refactor(rtcio): split rtcio/gpio switch with rtc iomux func sel func (v5.5)

See merge request espressif/esp-idf!48295
 2026-05-26 13:53:41 +08:00
Song Ruo Jing 58d883a99d fix(uart): lp uart rx iomux pin was not working as expected 
Introduced in 8818157e42
The workaround in the commit routes the signal to LP GPIO matrix first.
When uses LP IOMUX pin as UART RX, the signal did not bypass the matrix,
which caused the issue.

This commit adds rtc_gpio_iomux_input and rtc_gpio_iomux_output APIs
to align with existing GPIO driver APIs.
 2026-05-22 15:36:00 +08:00
Song Ruo Jing 5b7db25db1 refactor(rtcio): split rtcio/gpio switch with rtc iomux func sel func 
This allows rtc_gpio_deinit to always switch the pad back to GPIO,
regardless of lp io clock enabled or not, so that gpio_config can
always switch the IO back to GPIO use after wakeup from deep sleep.
 2026-05-22 15:35:21 +08:00