gen_crt_bundle.py now uses the shared esp-pylib library instead of its own
logging and argument parsing, so its messages look the same as the rest of
the ESP-IDF Python tools.
F_SETFL was replacing the whole flags word, so fcntl(fd, F_SETFL, O_APPEND)
made F_GETFL report O_RDONLY|O_APPEND. Keep O_ACCMODE and apply only POSIX
status flags.
Co-authored-by: Cursor <cursoragent@cursor.com>
fix(esp_wifi): Harden dpp Auth confirm and drop mismatched auth confirms
Closes WIFIBUG-2032 and WIFIBUG-2075
See merge request espressif/esp-idf!51554
- Gate bta_sys_event() on both 'is_reg' and 'reg[id]' to prevent
stale event delivery.
- Defer bta_sys_deregister() to the end of profile disable handlers
to ensure pending DISABLE events are processed.
- Add disabling flag to HFP AG for tracking asynchronous teardown.
Extend the CTR test data length to 6433 bytes so the trailing partial
block is exercised with external RAM buffers (which stalls the ESP32-S2
Crypto DMA on an unfixed driver), and add AES-GCM PSRAM tests verified
against internal RAM references.
The ESP32-S2 Crypto DMA in-channel stalls silently when a receive
descriptor list transitions from external to internal RAM. The AES
driver hits this when a PSRAM-output operation has a trailing partial
block, as the internal stream descriptor is linked after the external
RAM data descriptors.
- esp_aes_process_dma(): process the block-aligned part and the partial
block as two separate DMA operations, keeping each descriptor list
uniform
- crypto_dma_ll_reset(): also reset the in-channel (per the TRM receive
reset sequence), otherwise stale state from a preceding external-RAM
operation corrupts the next operation's output
The GCM DMA path is unaffected; it never operates on PSRAM buffers.
Both PSRAM layouts were mapped as a single RWX window, so everything in external
RAM - the heap included - was executable.
PSRAM used as data only is now RW, and under XIP-from-PSRAM it is split per
section as ESP32-P4 does: .text RX, .rodata read-only, and the MMU-page
alignment gaps and the reclaimed heap RW, so neither is executable.
Both describe the layout that esp_psram_init() produces, and the entries are
locked, so - again as on ESP32-P4 - they are only narrowed when
CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION says that layout applies. Without
it the application owns the region and PSRAM stays RWX.
The per-section entries cost one PMP entry more than the 16 available, so the CPU
subsystem and peripheral windows are chained as TOR entries, taking one entry
instead of three.
soc.h is corrected against the S31 bus address map: the peripheral window base
was 1 MB too low, and the LP peripheral top, derived from a register base plus a
size rather than from the map, was 16 KB short. SOC_NON_CACHEABLE_OFFSET_FLASH
is added.
Sort bond entries by bond_count after in-place updates to maintain correct
eviction order, and log IRK resolving-list failures instead of failing the bond.
Pranav Sonawane
Mahavir Jain
Rahul Tank
morris
Martin VychodilandCursor
wanckl
Jiang Jiang Jian
Chen Chen
wuzhenghui
Sergei Silnov
Jin Cheng
harshal.patil
Ashish Sharma
Shen Weilong
Daniel Paul
Fu Hanxi
Ivan Grokhotkov
Hu Rui
Wang Meng Yang
Evgeny Torbin
Euripedes Rocha