In components/soc/esp32c5/register/soc/gpio_ext_struct.h (ESP32-C5),
components/soc/esp32c61/register/soc/gpio_ext_struct.h (ESP32-C61),
and components/soc/esp32p4/register/hw_ver3/soc/gpio_struct.h
(ESP32-P4), the analog comparator raw/status/enable/clear register
fields are named comp_neg_0_*/comp0_neg_* for bit 0 and
comp_pos_0_*/comp0_pos_* for bit 1, but each field's own comment says
the opposite: bit 0 is documented as "analog comparator pos edge
interrupt raw/status/enable/clear" and bit 1 as the "neg" counterpart.
The LL masks were defined from the field names rather than from this
documented behavior, so ANALOG_CMPR_LL_POS_CROSS_INTR_MASK() ended up
selecting bit 1 and ANALOG_CMPR_LL_NEG_CROSS_INTR_MASK() bit 0.
A new test case, added in the following commit, arms only one cross
direction at a time and checks that a matching transition fires the
callback while the opposite, never-armed direction does not; without
this fix it reproducibly fails on ESP32-C5, ESP32-P4, and ESP32-C61.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
Define per-target SDIO slave descriptor buffer limits in the LL layer and validate queued send buffers against the 4-byte aligned effective maximum. Update the public docs to describe the chip-dependent limit instead of hardcoding 4092 bytes.
Co-authored-by: Cursor <cursoragent@cursor.com>
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.
PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
In release/v5.x, esp_fault.h resides in the esp_hw_support (G1)
component, so the G0 components (hal, esp_rom) must not depend on it.
Copy its contents to esp_common as esp_fault_internal.h, keep
esp_fault.h as a compatibility wrapper around it, and switch the hal
and esp_rom ECDSA/ECC code to the internal header.
The addend in `emac_hal_ptp_start()` was derived from the floating-point
`config->ptp_req_accuracy_ns` instead of the integer `base_increment`
register that actually drives the sub-second update. The cast to
`uint8_t` loses the fractional part, so the un-corrected addend leaves
the PTP clock running off-rate.
Example: with a 40 MHz XTAL and the default `req_accuracy_ns = 40`,
`base_increment` rounds 85.899 up to 86, leaving the clock +1170 ppm
fast — well outside the IEEE 802.1AS neighborRateRatio limit (~±200
ppm), so strict-1AS bridges refuse asCapable.
Compute the addend from the stored `base_increment` for both rollover
modes: `addend = 2^32 * clk_period_ns / increment_ns`.
Measured on ESP32-P4: neighborRateRatio drops from +1147.5 ppm to
+4.2 ppm, and asCapable is granted.
Co-authored-by: Ondrej Kosta <panzer412@gmail.com>
gaoxuandCursor
Song Ruo Jing
morris
Jiang Jiang Jian
Tiago Medicci
wanckl
Mahavir Jain
Chen Jichang
sibeibei
wuzhenghui
harshal.patil
JiangGuangMingandCursor
Scramble ToolsandOndrej Kosta