Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-09-30 02:00:51 +03:00
Code Issues Packages Projects Releases Wiki Activity
48,949 Commits 25 Branches 192 Tags
39e7e142f7da080ee77cb97fc6358e4e6dbd5fc3
Commit Graph
911 Commits
Author SHA1 Message Date
Armando (Dou Yiwen) b5f97b22e7 feat(flash): p4 flash 120MHz is no longer experimental feature 
Signed-off-by: Armando (Dou Yiwen) <douyiwen@espressif.com>
 2026-08-14 06:10:25 +00:00
C.S.M 6f14740263 fix(spi_flash): Fix spi_flash leaks release aes-xts in error path 
(cherry picked from commit 305c5869ee)
 2026-07-24 14:52:19 +08:00
Shengyu Qu dd99b5a272 fix(spi_flash): add #if check for s_mxic_set_required_regs() 
Currently, s_mxic_set_required_regs() lacks checking for
CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP. And this causes a defined but not
used warning when MXIC flash driver is disabled in project config. So add
a #if check for this to supress warning.

Signed-off-by: Shengyu Qu <wiagn@4d2.org>
(cherry picked from commit 062c948c18)
 2026-07-24 14:52:19 +08:00
harshal.patil 024de60208 fix(esp_common/esp_fault): make ESP_FAULT_ASSERT survive optimization 
ESP_FAULT_ASSERT(C) was silently deleted by the optimizer when C is a cached
flag/status already proven by a preceding `if (!C) return/goto`: the compiler
folds C to a constant and drops all three checks, removing the fault-injection
protection with no warning.
 2026-06-22 11:20:04 +05:30
Song Ruo Jing cec524c576 fix(spi_flash): gpspi flash clock could reach higher frequency 2026-06-09 22:08:32 +08:00
C.S.M ca66efe272 fix(spi_flash): Fix flash hpm build failure, 
Closes https://github.com/espressif/esp-idf/issues/18535
 2026-05-25 16:01:44 +08:00
Konstantin Kondrashov 7d5df005d2 fix(test_apps): Increase CONFIG_PARTITION_TABLE_OFFSET to 0x9000 
Fix some test apps that have a partition table offset of 0x8000,
which left no room for the bootloader for some chips.
 2026-05-13 10:29:04 +03:00
Xiao Xufeng 6affa18a26 fix(spi_flash): fixed overboundary check skipping of erase and write_encrypted 2026-04-22 02:31:06 +08:00
Xiao Xufeng b4de5a7af2 refactor(spi_flash): not patching api_funcs on C3 and S3 2026-04-22 02:31:06 +08:00
Xiao Xufeng 5cbeaaf7f9 refactoring(spi_flash): Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h 
- Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
  MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
- Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
- Update usage in clk_utils.c and esp_flash_spi_init.c
- Remove old macro from all soc_caps.h files
 2026-04-22 02:31:06 +08:00
morris 5736a2d132 Merge branch 'fix/32mb_120m_v5.5' into 'release/v5.5' 
fix(spi_flash): 1. Fix flash 120m in qio mode failed on esp32p4 (with 32M map enabled) 2. Add C61 32M flash support (backport v5.5)

See merge request espressif/esp-idf!46044
 2026-04-20 13:30:14 +08:00
Song Ruo Jing ccbf0abb7a fix(flash): flash erase operation may fail to raise PMS exception 2026-04-13 14:40:39 +08:00
C.S.M a033efcb3d fix(spi_flash): Fix esp32p4 120m flash suspend failed 2026-04-07 18:06:40 +08:00
armando 115d6d3749 fix(mmap): added 24bit addr check 2026-03-16 01:43:59 +00:00
Song Ruo Jing 5698be672b feat(mspi): support 120MHz flash and psram for esp32c61 2026-03-13 16:27:17 +08:00
Jiang Jiang Jian d892b1871c Merge branch 'feat/c5_flash_psram_timing_tuning_120m_v5.5' into 'release/v5.5' 
mspi: supported psram & flash 120MHz timing tuning on C5 (v5.5)

See merge request espressif/esp-idf!45878
 2026-03-13 15:48:34 +08:00
armando 453660968b feat(mspi): supported psram & flash 120MHz timing tuning 2026-03-13 11:12:45 +08:00
wuzhenghui 9fe9b83ab9 fix(esp_rom): sync spi_flash_disable/enable_cache patches to rom implementation 2026-03-10 14:16:37 +08:00
Fu Hanxi 124a1d3b82 ci: backport master to 5.5 2026-02-25 11:38:38 +01:00
morris 980e8289a1 refactor(tests): add missing sdkconfig files in the driver test 2026-01-07 10:18:58 +08:00
armando 46ae86b4cf fix(cache): fixed cache sync ops concurrent call issue 
Closes https://github.com/espressif/esp-idf/issues/18023
 2025-12-25 09:57:57 +08:00
Xiao Xufeng 27f1484774 test(esp_flash): fixed test config that c5 not support 120MHz 2025-12-17 12:16:55 +08:00
Xiao Xufeng faf6cc4f84 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 03:33:29 +08:00
Mahavir Jain 9ab736cbd1 fix(spi_flash): limit CPU clock to 160MHz for encrypted flash writes 2025-12-17 03:33:29 +08:00
C.S.M 8d5ae41df3 feat(spi_flash): Support flash suspend on esp32p4 resivion 3 2025-10-22 19:31:16 +08:00
morris 695f8e46d6 Merge branch 'fix/make_bootloader_flash_size_correct_v5.5' into 'release/v5.5' 
fix(bootloader_flash): Make bootloader flash size accurate , etc. (backport v5.5)

See merge request espressif/esp-idf!41706
 2025-10-20 14:21:40 +08:00
C.S.M 1bbffc5998 fix(spi_flash): Fix spi flash qio/dio read failed on gpspi flash 2025-10-14 17:45:29 +08:00
C.S.M 4016917f28 fix(spi_flash): Fix spi_flash clock for gpspi on esp32c5/p4 2025-10-14 17:45:29 +08:00
C.S.M ff1c10e385 refactor(spi_flash): Refactor gpspi flash for making it's clock accurate 2025-10-14 17:45:29 +08:00
armando e6d4eec507 feat(p4): p4 rev3 real chip support 2025-10-13 15:25:23 +08:00
C.S.M cfe8d1fb66 feat(spi_flash): Add support for gd55f flash chip 2025-07-30 17:31:16 +08:00
Jiang Jiang Jian 536a807665 Merge branch 'bugfix/esp_flash_escape_checking_v5.5' into 'release/v5.5' 
fix(esp_flash): fixed issue of escaping boundary check (v5.5)

See merge request espressif/esp-idf!40117
 2025-07-22 17:16:49 +08:00
Jiang Jiang Jian 3c39b32195 Chip/support esp32c61 v5.5 2025-07-22 12:21:36 +08:00
Xiao Xufeng da939fa729 fix(esp_flash): fixed issue of escaping boundary check 
Also patched corresponding ROM functions
 2025-06-25 01:35:21 +08:00
Shen Meng Jing 62d4115e08 docs: Fix some typos 2025-04-30 18:35:39 +08:00
Michael (XIAO Xufeng) e65efb9156 Merge branch 'test/enable_xip_mmap_cases' into 'master' 
fix(mmap): fixed cache2phys and phy2cache not patched when XIP on PSRAM

Closes IDF-10983

See merge request espressif/esp-idf!33629
 2025-04-16 15:30:23 +08:00
Xiao Xufeng e97b1a8b51 fix(mmap): fixed cache2phys and phy2cache not patched when XIP on PSRAM 2025-04-11 11:02:11 +08:00
Xiao Xufeng 477af3b4a8 ci(mmap): enable mmap and XIP related cases for c5 2025-04-11 11:02:11 +08:00
C.S.M 15fa7843ae refactor(spi_flash): Add spi_flash driver list linked check 2025-04-10 15:36:11 +08:00
Jiang Jiang Jian da316111c9 Merge branch 'fix/fix_l2_cache_miss_issue' into 'master' 
cache: fixed l2 cache suspended/frozen but l1cache triggers l2 writeback issue

Closes IDF-12717

See merge request espressif/esp-idf!37967
 2025-04-03 19:50:26 +08:00
wanckl 8994f8fe70 feat(spi_flash): add support gpspi ext_flash 2025-04-03 11:27:13 +08:00
armando 46be72437b fix(cache): fixed l2 cache suspended/frozen but l1cache triggers l2 writeback issue 2025-04-02 18:03:43 +08:00
Chen Ji Chang c3a3cc8657 Merge branch 'feat/h4_enable_ci_build' into 'master' 
feat(esp32h4): enable ESP32H4 ci build

Closes IDF-12332

See merge request espressif/esp-idf!37921
 2025-03-31 23:49:48 +08:00
Chen Jichang 1785e1d329 refactor(flash): spilt flash cap in esp_rom 2025-03-28 15:04:25 +08:00
Song Ruo Jing b38ac5ad82 feat(uart): add uart_detect_bitrate_bps API for data line bitrate measurement 
Closes https://github.com/espressif/esp-idf/issues/14721
 2025-03-28 15:03:19 +08:00
Chen Jichang 6c4271d4bb feat(esp32h4): disable unsupported build 2025-03-28 14:41:29 +08:00
Chen Jichang c34b4eb882 feat(esp32h4): enable ESP32H4 ci build 2025-03-28 14:41:28 +08:00
Armando (Dou Yiwen) 64ff6ec274 Merge branch 'fix/mutex_between_oct_flash_and_flash_rom_impl' into 'master' 
flash: mutex between oct flash and flash rom impl

See merge request espressif/esp-idf!37760
 2025-03-21 14:51:08 +08:00
Armando (Dou Yiwen) ee5042095b Merge branch 'refactor/psram_structure_refactor' into 'master' 
refactor(psram): cleanup psram component code structure

See merge request espressif/esp-idf!37870
 2025-03-21 00:52:03 +08:00
armando 9b845f9f8b fix(flash): mutex between flash rom impl and flash opi 2025-03-20 15:32:21 +08:00