Commit Graph
183 Commits
Author SHA1 Message Date
morris e04875807d Merge branch 'fix/esp_psram_init_fix_v5.5' into 'release/v5.5'
fix(esp_psram): repeated call to init should return invalid state error (v5.5)

See merge request espressif/esp-idf!50275
2026-07-21 10:37:42 +08:00
Jiang Jiang Jian cc5a3fbcb5 Merge branch 'feat/psram_enc_exempt_v5.5' into 'release/v5.5'
feat(esp_psram): add option to carve unencrypted PSRAM region (v5.5)

See merge request espressif/esp-idf!49931
2026-07-16 17:04:28 +08:00
wuzhenghui 1b3d83528b change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT caps 2026-07-09 17:33:25 +08:00
Renz Bagaporo 4cf3f9c108 fix(esp_psram): repeated call to init should return invalid state error
Closes https://github.com/espressif/esp-idf/issues/18722
2026-07-02 09:55:57 +09:00
Mahavir Jain 6d51abfc4c docs(esp_psram): clarify carve-out location is at upper end of PSRAM
The previous wording "top of PSRAM" was ambiguous: the carve-out is
actually mapped at the highest physical addresses of PSRAM (after the
rodata, text, and main heap mappings). Update the Kconfig help text for
SPIRAM_ENC_EXEMPT and SPIRAM_ENC_EXEMPT_SIZE, the External RAM
documentation, and the internal layout comment to say "upper end of PSRAM
(highest physical addresses)" instead.
2026-06-23 14:56:41 +05:30
Mahavir Jain afdf1a5259 feat(esp_psram): add esp_psram_ptr_is_no_enc() helper
Drivers that allocate from the unencrypted PSRAM carve-out via
MALLOC_CAP_SPIRAM_NO_ENC currently have no way to verify after the fact
which pool a buffer came from. This is particularly relevant for callers
using heap_caps_malloc_prefer(MALLOC_CAP_SPIRAM_NO_ENC, MALLOC_CAP_SPIRAM),
where a silent fallback to encrypted PSRAM would still pass the typical
esp_ptr_external_ram() check.

Expose esp_psram_ptr_is_no_enc() in the public esp_psram.h header. It
performs a range check against the carve-out's virtual-address window and
returns false when PSRAM is not initialized or CONFIG_SPIRAM_ENC_EXEMPT is
disabled, so callers do not need to guard the call site with #if.

Also reference the helper from the External RAM documentation alongside
the heap_caps_malloc(MALLOC_CAP_SPIRAM_NO_ENC) usage example.
2026-06-23 14:56:40 +05:30
Mahavir Jain 656a5857eb fix(esp_psram): handle carve-out vaddr exhaustion and add region to self-test
If the virtual-address pool is exhausted when reserving the unencrypted
PSRAM carve-out (the warning at L388 may already have fired for the main
mapping), esp_mmu_map_reserve_block_with_caps() returns an error rather
than aborting. Convert the previous assert() into a logged fallback that
disables the carve-out for this boot, mirroring the SPIRAM_ENC_EXEMPT_SIZE
>= psram_available_size path.

Also extend esp_psram_extram_test() to run the standard memory test on
the carve-out region when CONFIG_SPIRAM_ENC_EXEMPT is enabled, so the
unencrypted mapping is exercised on startup like the other PSRAM regions.
2026-06-23 14:56:40 +05:30
harshal.patil 1fde0259fe change(esp_psram): Consider all PSRAM regions in PMP protection 2026-06-23 14:56:39 +05:30
Mahavir Jain ba69281a01 docs(esp_psram): document MALLOC_CAP_SPIRAM_NO_ENC carve-out
Extends the External RAM encryption section to describe
CONFIG_SPIRAM_ENC_EXEMPT and the MALLOC_CAP_SPIRAM_NO_ENC heap
capability, including a security warning and a typical DMA-alignment
use case. Mirrors the change in zh_CN.
2026-06-23 14:56:39 +05:30
Mahavir Jain 0044542811 feat(esp_psram): add option to carve unencrypted PSRAM region
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
2026-06-23 14:56:38 +05:30
wuzhenghui ddddb4d25c feat(esp_psram): wakeup PSRAM by CE# force control instead of dummy write 2026-06-18 16:06:00 +08:00
wuzhenghui 33f5b9a5fb feat(esp_hw_support): check psram data is not corrupted after lightsleep 2026-06-18 16:06:00 +08:00
Song Ruo Jing 6079c74f99 feat(psram): allow PSRAM to enter halfsleep mode during light sleep 2026-06-18 16:05:49 +08:00
Xiao Xufeng be62da6ca4 fix(mspi): fixed possible boot failure in some builds when psram is enabled
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
2026-05-19 23:55:01 +08:00
Marius Vikhammer d3a1700039 docs: clarify PSRAM default allocation behavior
Clarify that MALLOC_CAP_DEFAULT describes a memory capability
rather than the malloc() placement policy, so PSRAM-backed
capability allocations are documented correctly when malloc()
remains internal-only by default.

Closes https://github.com/espressif/esp-idf/issues/18391

Made-with: Cursor
2026-03-27 10:05:54 +08:00
Song Ruo Jing 5698be672b feat(mspi): support 120MHz flash and psram for esp32c61 2026-03-13 16:27:17 +08:00
armando 453660968b feat(mspi): supported psram & flash 120MHz timing tuning 2026-03-13 11:12:45 +08:00
Xiao Xufeng d5ecb0b27f fix(psram): cleanup PSRAM_MSPI_MB_WORKAROUND to avoid future issue 2026-03-06 19:49:06 +08:00
morris 272e620c62 Merge branch 'change/change_to_only_do_v2p_once_when_startup_v5.5' into 'release/v5.5'
mmu: no longer disable cache when converting virtual addr to physical addr and vice versa (v5.5)

See merge request espressif/esp-idf!45476
2026-03-02 11:29:49 +08:00
armando 58c57da9f8 test(mspi): add flash api run on psram stack test for xip_psram case 2026-02-09 07:28:22 +00:00
Alexey Lapshin 1c08b38b27 feat(build): propagate compiler flags from files to toolchain.cmake
This change improves build consistency across external projects integrated
through CMake by ensuring that compiler flags defined in configuration files
are passed correctly to the toolchain. It covers the majority of use cases,
as external projects are typically also CMake-based. For projects that use
a custom build system, users will still need to specify the required flags
manually.
2026-01-30 17:30:49 +07:00
Xiao Xufeng bb79e6f246 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-19 17:53:51 +08:00
morris 9e1c0fc4ee Merge branch 'fix/psram_encryption_warning_c5c61_v5.5' into 'release/v5.5'
fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on... (v5.5)

See merge request espressif/esp-idf!44622
2026-01-16 09:58:25 +08:00
armando 67a1e80e51 fix(mspi): fixed mspi dma burst timing issue 2026-01-15 14:11:05 +08:00
Xiao Xufeng a4aff97a21 fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on ESP32-C5 v1.2 and C61 v1.1 2026-01-13 18:00:18 +08:00
armando ffcf9f3330 change(psram): use 200M as default 2025-11-18 11:06:23 +08:00
Armando b698ac758e feat(psram): support 250MHz in experimental 2025-11-14 09:34:51 +08:00
Mahavir Jain d32b70d552 fix(esp_psram): make SPIRAM_USE_MEMMAP available for all targets
This reverts earlier commit d2858847 and thereby making SPIRAM_USE_MEMMAP
available for all targets.

This config option has no direct usage but just avoids adding the PSRAM
to heap but still keeps it memory mapped.

Closes https://github.com/espressif/esp-idf/issues/17764
2025-11-05 14:07:22 +05:30
armando 7b9f5b85a7 fix(psram): fixed p4 rev3 xip stuck after board reset issue 2025-10-23 17:00:24 +08:00
armando 17a23d1ddb fix(psram): fixed psram cross page issue 2025-08-22 00:02:06 +08:00
Mahavir Jain 29df7286c8 fix(esp_psram): make SPIRAM_USE_MEMMAP depend on ESP32 target 2025-08-11 13:46:39 +05:30
Mahavir Jain 2829481eb6 fix(psram): provide boot warning about PSRAM encryption issue on C5/C61
For C5/C61 revision 1.0, PSRAM encryption has hardware issue. This will
be addressed in future silicon version. Add explicit warning about this.
2025-08-11 13:46:38 +05:30
armando 44eba53113 feat(psram): support fallback to use default driver pattern when id isn't match 2025-06-23 10:15:59 +08:00
morris 1a40b106b4 Merge branch 'fix/fix_xip_psram_ptr_check_v5.5' into 'release/v5.5'
psram: fixed psram ptr check issue under xip_psram condition for ESP32P4 (v5.5)

See merge request espressif/esp-idf!39732
2025-06-17 10:34:10 +08:00
morris 56a4c70c31 Merge branch 'change/psram_2t_check_only_on_ap_v5.5' into 'release/v5.5'
psram: limited 2t check only for ap (v5.5)

See merge request espressif/esp-idf!39429
2025-06-17 10:30:51 +08:00
armando 30d77f494e fix(psram): fixed psram ptr check under xip_psram condition
Closes https://github.com/espressif/esp-idf/pull/15999
Closes https://github.com/espressif/esp-idf/issues/15997
2025-06-11 06:44:21 +00:00
John Boiles 7557ec0951 fix(memory-utils): Add _instruction_reserved_start/end to esp_psram_check_ptr_addr
Adds missing range check that can be used when SPIRAM_XIP_FROM_PSRAM is enabled.
2025-06-11 06:44:21 +00:00
armando 5961670d06 change(psram): limited 2t check only for ap 2025-06-05 02:50:08 +00:00
armando 3092578b4a fix(ci): fixed psram tests not running on c5 issue 2025-05-22 14:42:48 +08:00
harshal.patil 3123fff18a fix(esp_psram): Add XIP PSRAM alignment gaps in heap only if PSRAM protection is enabled 2025-05-05 10:50:19 +05:30
Harshal Patil d898c2398b Merge branch 'feat/some_xip_psram_related_optimisations_and_fixes' into 'master'
feat(esp_psram): Fix late PSRAM init and add some wasted XIP PSRAM memory in heap

Closes IDF-11463 and IDF-10555

See merge request espressif/esp-idf!37116
2025-04-30 00:02:19 +08:00
harshal.patil 003b54ebfe feat(esp_psram): XIP from PSRAM can be used only when SPIRAM_BOOT_INIT=y for ESP32P4
In case of ESP32-P4, if SPIRAM memory initialisations are not performed during
boot-up, XIP PSRAM can be setup because of different virtual range of PSRAM and Flash
2025-04-29 11:48:28 +05:30
harshal.patil c67901fc07 ci(esp_psram): Add a test to validate non-bootup PSRAM initialisation
- Also adds a test for the newly added PSRAM helper APIs:
esp_psram_get_heap_pool_size() and esp_psram_get_effective_mapped_size()
2025-04-29 11:48:28 +05:30
harshal.patil f58c78b644 fix(esp_psram): Fix loading PSRAM XIP segments after PMP split has been configured 2025-04-29 11:48:27 +05:30
harshal.patil ab229a34b3 feat(cpu_region_protect): Enable basic memory protection for SPIRAM 2025-04-29 11:48:27 +05:30
harshal.patil 49f253361e feat(esp_psram): Add the gap created due to alignment of XIP segments in heap 2025-04-29 11:48:27 +05:30
harshal.patil 0f628496c8 feat(esp_psram): Add some helper APIs to get usable PSRAM memory size 2025-04-29 11:48:27 +05:30
harshal.patil 46225a4026 feat(esp_psram): Add a new API to just detect and enable the PSRAM
- esp_psram_chip_init() just detects and does basic initialisations of PSRAM
- esp_psram_init() initialises and maps/loads the PSRAM pages
2025-04-29 11:48:27 +05:30
armando 00e256d343 fix(psram): fixecd wrong ap density check 2025-04-28 16:10:18 +08:00
armando 89d566bb9c fix(psram): fixed psram init state not in low speed mode issue on c5 c61 2025-04-27 15:06:40 +08:00