Move the cache profile counter type definitions to hal/cache_types.h so
that
esp_cache_cnt.h can use them without depending on the public soc header
soc/cache_periph.h (which CI rejects as non-public).
The remaining cache_periph.h header and its per-target cache_periph.c
sources
are moved from the soc component into the hal component, with the
sources
organized per target directory as usual for the hal component.
Removes the soc/cache_periph.h dependency from esp_cache_cnt.h and
hal/cache_ll.h by using hal/cache_periph.h instead.
On ESP32-S3, USB PHY is clocked from BBPLL,
however if the BBPLL is not used as CPU clock source,
the power management unit can turn it off.
This commit registers USB as BBPLL consumer so it is not turned off.
Closes https://github.com/espressif/esp-idf/issues/15451
The critical section port already disables interrupts and reads the core id for
the whole section, but spinlock_acquire()/spinlock_release() then disabled
interrupts again to the same level and re-read the core id register.
Add spinlock_acquire_impl()/spinlock_release_impl(), which take a caller-supplied
owner id and skip interrupt management, and reuse them from
spinlock_acquire()/spinlock_release() to avoid duplicated code. The Xtensa and
RISC-V ports now read the core id once and call the impl variants, removing one
core id read and one interrupt mask/restore per critical section enter and exit.
Closes https://github.com/espressif/esp-idf/issues/18908
Move soc_etm_retention_desc_t type definition and soc_etm_retention_info
data from hal component to esp_hw_support component, following the
pattern of other peripheral retention data (e.g. MWDT).
- Create esp_private/etm_retention.h with type and extern declaration
- Create port/<target>/etm_retention.c for each target with retention data
- Remove hal/<target>/etm_periph.c and hal/include/hal/etm_periph.h
- Update esp_etm.c to include the new header
- Update CMakeLists.txt in both components
fix(components): linux host-build failure fixes+ disable esp_tee in buildv2 + esp_hw_support and xtensa fixes
See merge request espressif/esp-idf!48743
Moved the linux spinlock.h stub into esp_hw_support/include/linux.
esp_hw_support's INCLUDE_DIRS already places include/linux before
include, so the correct include files are picked up for the linux
target.
- Drop the FreeRTOS-Kernel-SMP linux spinlock.h duplicate.
- rv_decode_test: use PRIV_REQUIRES esp_hw_support instead of
hardcoding component include paths.
1) Add support for MAC randomization in Active scan and connect
2) Add support for randomizaton of sequence numbers
3) Add support for randomization of dialog token for GAS frames
spinlock.h used #else to include riscv/rv_utils.h for all non-Xtensa
targets. On Linux host (neither __XTENSA__ nor __riscv defined), this
pulls in a non-existent header. Change to #elif __riscv, matching
esp_cpu.h's existing pattern.
Add a generic derived-PLL clock engine to esp_clk_tree_common that
handles acquire/release, mux selection, and divider programming for
target-defined derived clocks. Per-target descriptors (ESP32-P4,
ESP32-S31) plug into the engine via
esp_clk_tree_get_derived_clk_desc().
