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48,436 Commits 25 Branches 192 Tags
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3603 Commits
Author SHA1 Message Date
Jack 02d9e2d0c3 Revert "disable PVT feature for esp32c5" 
This reverts commit bfb052dbac.
 2026-07-06 20:25:47 +08:00
Jiang Jiang Jian 9098c60919 Merge branch 'bugfix/fix_some_wifi_bugs_260617_v5.5' into 'release/v5.5' 
fix(wifi): fix some wifi bugs 260617 backport v5.5

See merge request espressif/esp-idf!49777
 2026-06-22 20:38:53 +08:00
Chen Jichang 1096a381a9 change(ahb_dma): update c61 eco3 header files 2026-06-22 11:15:25 +08:00
sibeibei d4166e94d8 fix(wifi): fix modem sleep flag clear failed 2026-06-18 18:09:56 +08:00
Jiang Jiang Jian e8d8197b5a Merge branch 'fix/move_system_retention_to_esp_hw_support_v5.5' into 'release/v5.5' 
refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support (v5.5)

See merge request espressif/esp-idf!49751
 2026-06-18 11:27:44 +08:00
Jiang Jiang Jian ad91c6ed0f Merge branch 'feat/support_usb_wakeup_v5.5' into 'release/v5.5' 
feat: support usb as wakeup source from light sleep (v5.5)

See merge request espressif/esp-idf!49511
 2026-06-17 19:50:18 +08:00
wuzhenghui bf4a668089 refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support 2026-06-17 12:21:41 +08:00
Jiang Jiang Jian 87c540da31 Merge branch 'fix/disable_secure_boot_v2_ecdsa_v5.5' into 'release/v5.5' 
Fix/disable secure boot v2 ecdsa (v5.5)

See merge request espressif/esp-idf!49472
 2026-06-17 12:00:48 +08:00
Jiang Jiang Jian 510488345c Merge branch 'fix/esp_idf_lp_uart_wakeup_muti_times_v5.5' into 'release/v5.5' 
fix(ulp): fix lp uart keep wakeup triggered v5.5

See merge request espressif/esp-idf!49401
 2026-06-17 11:59:15 +08:00
hebinglin ab7f6a6d95 fix(ulp): fix lp uart keep wakeup triggered 2026-06-15 15:18:31 +08:00
JiangGuangMingandCursor 3b32b1fc96 feat(sleep/usb): support usb as wakeup source from light sleep 
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-06-11 09:05:40 +08:00
Aditya Patwardhan 66156479d2 change(secure_boot): mark ECDSA based Secure Boot V2 as insecure on affected SoCs 
ECDSA based Secure Boot V2 is not functional for certain input vectors on
ESP32-C5/C61/H2/P4 and on the preview targets ESP32-H4/H21. RSA based Secure
Boot V2 is the recommended scheme where the SoC supports it. This issue will be
fixed in a future hardware ECO revision; more details will be shared through the
hardware errata document.

A new hidden Kconfig option SECURE_BOOT_V2_ECDSA_INSECURE marks the affected
mass-production SoCs (ESP32-C5/C61/H2/P4). On these SoCs, when hardware Secure
Boot V2 is enabled, the ECDSA (V2) signing scheme is no longer offered by
default; it must be turned on explicitly via SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
under "Allow potentially insecure options" (CONFIG_SECURE_BOOT_INSECURE). App
signing without hardware Secure Boot is not affected. Note that ESP32-C61 has no
RSA based Secure Boot V2, so it has no Secure Boot scheme enabled by default.

The preview targets ESP32-H4 and ESP32-H21 mark ECDSA Secure Boot V2 as not
supported in their SoC capabilities instead of using the option above. As
ESP32-H4 has no other Secure Boot V2 scheme, Secure Boot is disabled entirely on
it; ESP32-H21 retains RSA based Secure Boot V2.

The security documentation keeps the ECDSA Secure Boot V2 content visible and
adds a warning describing the limitation (including that ECDSA Secure Boot V2 on
ESP32-C61 is not recommended for production). CI apps that exercise ECDSA Secure
Boot V2 on the affected SoCs set CONFIG_SECURE_BOOT_V2_FORCE_ENABLE_ECDSA
accordingly.
 2026-06-10 08:08:07 +05:30
harshal.patil 673c861ac2 fix(soc): Remove non-existent crypto registers (ESP32-C61) 2026-06-09 18:18:13 +05:30
hebinglin 4a42a8847b fix(ulp): record wakeup causes before lp core request sleep 2026-06-01 21:11:48 +08:00
Chen Jichang 3dccd4b740 feat(lcd): support i80 lcd sleep retention on p4 2026-05-25 16:09:53 +08:00
sibeibei 45b690e465 bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source 2026-05-20 20:15:50 +08:00
Mahavir Jain 6a32889849 Merge branch 'feature/recovery_bootloader_support_v5.5' into 'release/v5.5' 
feat(bootloader): Support recovery bootloader for ESP32P4 (v5.5)

See merge request espressif/esp-idf!48474
 2026-05-19 12:35:57 +05:30
Konstantin Kondrashov ce467787a9 feat(bootloader): Support recovery bootloader for ESP32P4/C61 2026-05-13 10:28:58 +03:00
Konstantin Kondrashov 7a45d611e4 feat(efuse): Adds efuse calibration field for esp32c5 2026-05-07 16:00:29 +03:00
Jiang Jiang Jian 99967b607f Merge branch 'feature/efuse_adds_fields_v5.5' into 'release/v5.5' 
feat(efuse): Adds efuse flash fields for esp32c2 (v5.5)

See merge request espressif/esp-idf!45340
 2026-05-06 10:27:53 +08:00
Konstantin Kondrashov 13d9b43701 feat(efuse): Adds efuse flash fields for esp32c2 2026-05-01 12:21:15 +03:00
Konstantin Kondrashov 5561482b37 feat(efuse): Adds efuse for ESP32-H2 revision 1.2 2026-05-01 12:17:57 +03:00
morris 619f0c297a Merge branch 'feat/soc_usb_fsls_phy_num_backport_v5.5' into 'release/v5.5' 
feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets (backport v5.5)

See merge request espressif/esp-idf!47938
 2026-04-29 10:59:40 +08:00
Jiang Jiang Jian 7e61b7d980 Merge branch 'refactor/spi_flash_private_v5.5' into 'release/v5.5' 
fix(spi_flash): fixed overboundary check skipping of erase and write_encrypted (v5.5)

See merge request espressif/esp-idf!45657
 2026-04-28 11:08:43 +08:00
igor.masar a9822b0ad1 feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets 
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3 and ESP32-P4 to
expose the number of FSLS USB_WRAP PHYs available on each target. This
separates FSLS USB_WRAP support from OTG/UTMI support so that downstream
code can gate FSLS PHY handling independently.
 2026-04-24 12:40:17 +02:00
gaoxu e7c8f8fc8f fix(isp): fix isp clock source error 2026-04-24 11:04:48 +08:00
Xiao Xufeng 5cbeaaf7f9 refactoring(spi_flash): Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h 
- Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
  MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
- Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
- Update usage in clk_utils.c and esp_flash_spi_init.c
- Remove old macro from all soc_caps.h files
 2026-04-22 02:31:06 +08:00
morris 5736a2d132 Merge branch 'fix/32mb_120m_v5.5' into 'release/v5.5' 
fix(spi_flash): 1. Fix flash 120m in qio mode failed on esp32p4 (with 32M map enabled) 2. Add C61 32M flash support (backport v5.5)

See merge request espressif/esp-idf!46044
 2026-04-20 13:30:14 +08:00
Song Ruo Jing d15a897d13 feat(dma2d,ppa): Support flash encryption for DMA2D and PPA 2026-04-13 15:03:37 +08:00
Mahavir Jain 19731dd91a Merge branch 'fix/enable_key_mgr_clk_for_efuse_key_ops_v5.5' into 'release/v5.5' 
Support newer Key Manager key sources for ESP32-P4 V3 (v5.5)

See merge request espressif/esp-idf!46755
 2026-04-08 11:19:56 +05:30
C.S.M a033efcb3d fix(spi_flash): Fix esp32p4 120m flash suspend failed 2026-04-07 18:06:40 +08:00
harshal.patil 8dafc3b75f feat(esp32p4): Support newer Key Manager key sources for ESP32-P4 V3 2026-04-06 18:11:43 +05:30
Luo Xu 180cdf4eb0 feat(ble_mesh): restore ble mesh for esp32c5/c61 
(cherry picked from commit b2143d271e)

Co-authored-by: luoxu <luoxu@espressif.com>
 2026-04-02 16:31:59 +08:00
wanckl f9575867d8 feat(driver_twai): new driver sleep retention support 2026-04-01 10:56:32 +08:00
morris e4de37c194 Merge branch 'change/deprecate_tcm_and_use_scp_v5.5' into 'release/v5.5' 
tcm: deprecated tcm and added scp memory utils (v5.5)

See merge request espressif/esp-idf!46590
 2026-03-31 15:12:08 +08:00
Mahavir Jain dc112bb460 Merge branch 'fix/esp32c61_rom_stack_addr_v5.5' into 'release/v5.5' 
fix(soc): Correct the ESP32-C61 ROM stack start address (v5.5)

See merge request espressif/esp-idf!47151
 2026-03-31 10:55:50 +05:30
morris c8b20a8099 Merge branch 'bugfix/lp_io_clock_control_v5.5' into 'release/v5.5' 
fix(rtcio): RTC GPIO configuration should be written if LP IO clock exists (v5.5)

See merge request espressif/esp-idf!46601
 2026-03-31 10:27:25 +08:00
armando 0cb42beabf fix(spm): rename scp (scratchpad) to spm (scratchpad memory) 2026-03-31 09:24:53 +08:00
armando 55c462ccab change(mem): deprecated tcm and added scp memory utils 2026-03-31 09:22:11 +08:00
Alexey Gerenkov 414791d955 Merge branch 'feature/enable_misalign_optimization_for_iperf_v5.5' into 'release/v5.5' 
feat(newlib): enable libc misalign optimized functions (v5.5)

See merge request espressif/esp-idf!42676
 2026-03-31 00:49:02 +08:00
Laukik Hase d3300de850 fix(soc): Correct the ESP32-C61 ROM stack start address 2026-03-30 18:30:29 +05:30
Mahavir Jain ff249f532f Merge branch 'bugfix/external_mem_enc_docs_v5.5' into 'release/v5.5' 
docs: update PSRAM and flash encryption docs with per-page and separate key capabilities (v5.5)

See merge request espressif/esp-idf!46956
 2026-03-30 11:46:30 +05:30
Jiang Jiang Jian 0a981c10cd Merge branch 'feat/support_rv_fp_retention_v5.5' into 'release/v5.5' 
feat(esp_hw_support): support rv fp retention (v5.5)

See merge request espressif/esp-idf!46522
 2026-03-30 14:07:53 +08:00
Mahavir Jain 1b9b001f23 docs: update PSRAM and flash encryption docs with per-page and separate key capabilities 2026-03-24 12:54:59 +05:30
Alexey Lapshin 9332d2ccd2 fix(newlib): fix CONFIG_LIBC_OPTIMIZED_MISALIGNED_ACCESS for c2/c3/c6/h2/h21 
PMP configurations for load and store addresses may
have different permissions (e.g., "R" vs. "RW").

Due to the timing alignment of internal signals, the address
permission check may be incorrectly applied during the second
part of a misaligned access transaction.

As a workaround, insert two instructions (e.g. ADDI/NOP) between
accessing to different memory regions. This spacing avoids the
false permission check caused by signal timing overlap.
 2026-03-20 12:59:12 +07:00
Song Ruo Jing 5698be672b feat(mspi): support 120MHz flash and psram for esp32c61 2026-03-13 16:27:17 +08:00
Song Ruo Jing ae99294ea3 fix(rtcio): RTC GPIO configuration should be written if LP IO clock exists 2026-03-13 14:24:42 +08:00
wuzhenghui 5ed166e97f feat(esp_hw_support): support esp32p4 RV FPU context retention in pd_cpu sleep 2026-03-12 11:37:10 +08:00
Jiang Jiang Jian 9bb162e7ae Merge branch 'bugfix/esp_idf_s3_deepsleep_dead_v5.5' into 'release/v5.5' 
fix(hal): fix the issue of dual-core contention for RTC_CNTL regs (v5.5)

See merge request espressif/esp-idf!46171
 2026-03-07 11:18:24 +08:00
Jiang Jiang Jian a650e6c21b Merge branch 'bugfix/fixed_blufi_doc_issue_v5.5' into 'release/v5.5' 
fix(doc): set SOC_BLUFI_SUPPORTED in soc_caps.h for ESP32-C5 (v5.5)

See merge request espressif/esp-idf!45414
 2026-03-07 11:03:56 +08:00