Legacy ulp_embed_binary() call-site sources were attached directly to the CMake v2 child executable. However, the ULP runtime is linked with WHOLE_ARCHIVE through target_link_options(), which CMake emits before executable objects. This reversed the CMake v1 order, changed ULP code placement, and allowed runtime weak definitions to take precedence over legacy strong handlers.
Build the call-site sources as a dedicated static archive and place its whole-archive option before the runtime archive. Preserve the parent sdkconfig and include view, including FSM-specific include behavior, without generating a synthetic component tree.
Factor linker-specific whole-archive handling into a shared CMake v2 helper for GNU, Darwin, and ULP FSM linkers. Link the archive target normally as well so CMake tracks build and relink dependencies when a legacy ULP source changes.
Expose RC_FAST as a shared MCPWM group clock source for timers,
capture timers, and carriers on ESP32-C5, ESP32-C6, ESP32-H2,
and ESP32-P4. Fix the ESP32-S31 MCPWM clock selector mapping.
Add a hardware runtime test that verifies MCPWM Timer counting
resolution for every supported clock source.
Add test apps for binary size tracking:
- esp_timer size_metrics app with minimal/full sdkconfig variants
- minimal_baseline app to establish the platform binary size floor
- remmediate deep-review memory-saftey and DoS defects
- fix duplicated report of HCI mode change event
- fix conflicts in handling sniff subrate request when ACL link enters active mode
The PSRAM encryption anti-FI check in mmu_ll_write_entry() pulls in
ESP_FAULT_ASSERT and efuse_hal_chip_revision(), which inflate the
bootloader image size. The check is not meaningful in the bootloader
or in the ESP-TEE build, so guard it out for both.
Applies to esp32c5, esp32c61 and esp32p4.
The second stage bootloader no longer configures or locks PMP entries on
C5, C6, C61, H2 and P4; document the impact on non-ESP-IDF applications
launched by the ESP-IDF bootloader that relied on the bootloader-provided
PMP configuration.
Commit ab229a34 added PSRAM memory protection for ESP32-P4 rev < 3.0. It
consumed all 16 PMP entries and shifted the fixed LP-RAM (9-12 -> 11-14) and
peripheral (13 -> 15) entries to make room. Older bootloaders lock the
peripheral entry at its original index 13, so on a v5.3/v5.4 bootloader running
a newer application the LP-RAM entry that landed on the locked index 13 was
silently ignored, weakening LP-RAM protection.
Select the rev < 3.0 layout at runtime by probing whether the bootloader locked
the peripheral at entry 13:
- locked (v5.3/v5.4) -> default layout (LP-RAM 9-12, peripheral 13), no PSRAM
protection; these devices never had it (it was introduced in v5.5).
- free (v5.5+) -> PSRAM layout (flash/ext-RAM 6-10, LP-RAM 11-14,
peripheral 15) with full external-RAM protection; the peripheral entry at 15
matches the bootloader's lock.
This restores forward compatibility across all shipped rev < 3.0 bootloaders
without regressing PSRAM protection on the v5.5+ devices that already have it.
Chip revision >= 3.0 (32 PMP entries) is unaffected.
A PMP entry the (non-OTA-updatable) bootloader locks cannot be reconfigured
by the application until CPU reset, so the layout of the entries a shipped
bootloader locks is a bootloader<->application ABI that renumbering would
silently break on deployed devices.
On C5, C6, C61, H2 and P4 the bootloader now configures only the PMA invalid regions
and leaves PMP to the application.
On C5 the application programs the two ROM entries without a cfg reset:
v6.0/v6.1 bootloaders lock the TOR base entry at SOC_IROM_MASK_LOW, so on
such devices the TOR region above it spans the ROM text and must keep the
X bit those bootloaders left in the following unlocked entry, which
OR-only writes can never clear. With newer bootloaders the application
receives clean entries and the ROM data region gets the intended strict R
permission.
Rename the internal ULP child-build marker to __ULP_BUILDV2 so component CMake files make the build-system scope explicit.
Document that the marker is currently set only by the IDF_BUILD_V2 ULP child path.
Route ulp_embed_binary() through a built-in CMake v2 default ULP project instead of generating a compatibility project with a synthetic main component.
Attach legacy ULP sources directly to the ULP executable, pass the parent component include view through the existing ULP_S_SOURCES/COMPONENT_* channel, and remove the generated legacy project templates plus the component path ownership validation bypass they required.
Update the build-system coverage to assert that the builtin child project builds and rebuilds when parent-owned ULP sources change.
Allow the reconfigure test to assert the buildv2 activation message when pytest runs with --buildv2.
Make the ULP API probe use CMake-friendly forward-slash paths and an explicit ULP toolchain/custom-toolchain setting so the direct cmake configure works on Windows as well as Linux.
Preserve all linker scripts passed to target_linker_script() so LP-core child builds keep the full esp32p4 LP ROM script set instead of only the first script.
Link the ULP runtime component as WHOLE_ARCHIVE for ULP child builds, matching the legacy helper behavior where runtime sources were added directly to the executable. This keeps strong runtime handlers such as ulp_lp_core_panic_handler from being skipped in favor of weak defaults from already-extracted archive objects.
Validated with the esp32p4 lp_core_hp_uart panic and LP-ROM pytest cases, plus the focused local/CI build_all shape for the app.
fix(bt): Fixed several issues on BR/EDR controller on ESP32-S31
Closes BTQABR2023-829, BTQABR2023-836, BTQABR2023-837, BTQABR2023-840, BTQABR2023-687, and BTQABR2023-697
See merge request espressif/esp-idf!51249
