Commit Graph

23 Commits

Author SHA1 Message Date
Renz Bagaporo
1f5cba3070 fix(ulp): clarify buildv2 child marker
Rename the internal ULP child-build marker to __ULP_BUILDV2 so component CMake files make the build-system scope explicit.

Document that the marker is currently set only by the IDF_BUILD_V2 ULP child path.
2026-07-29 13:08:23 +09:00
Alexey Lapshin
77420a6f78 Merge branch 'feature/use_zcmp_by_default' into 'master'
feat(build): add ZCMP workaround post-build check

See merge request espressif/esp-idf!49764
2026-07-28 14:00:37 +04:00
Alexey Lapshin
631ad9033c feat(build): add RISC-V ZCMP post-link workaround check
Validate linked RISC-V executables when
CONFIG_COMPILER_ENABLE_RISCV_ZCMP is enabled on affected chips.
Disassemble each function and reject mstatus.MIE clears that lack an
earlier mintthresh write of 0xff.

Handle csrrci, csrrw, and register-mask csrrc patterns while ignoring
csrrs. Add build-only coverage for valid and invalid sequences with
CMake v1 and v2.

Stop the hardware stack guard before switching stacks during restart,
and keep ZCMP disabled for TEE test apps that still require the
workaround.
2026-07-22 13:04:20 +07:00
morris
26a22512eb refactor(hal): extract assist_debug, debug_probe and trace into esp_hal_debug_assist
Move the following modules from the hal component into a new dedicated
esp_hal_debug_assist component, following the esp_hal_timg pattern:

- assist_debug (hal + target-specific LL headers)
- debug_probe (types + target-specific LL headers)
- riscv_trace (hal + types + source + target-specific LL headers)
- trace_ll (esp32/esp32s2/esp32s3 target-specific LL headers)

Update the following components to depend on esp_hal_debug_assist:
esp_system, riscv, bootloader_support, esp_hw_support, esp_riscv_trace

Remove riscv_trace_hal.c from the hal component.
2026-07-21 11:28:11 +08:00
Renz Bagaporo
7d75f85221 feat(ulp): build ULP full subprojects as CMake v2 children 2026-07-15 09:14:35 +09:00
Laukik Hase
340de9823a feat(esp_tee): Support for ESP32-C5 - the rest of the components 2025-08-13 14:08:59 +05:30
laokaiyao
db85cd02be refactor(esp32c61): bus_monitor backward compatible refactor 2025-04-08 22:50:04 +08:00
Laukik Hase
e51d2c1da3 feat(esp_tee): Support for ESP-TEE - riscv component 2024-12-02 12:20:04 +05:30
Omar Chebib
102d5bbf72 refactor(riscv): added a new API for the interrupts 2024-01-18 16:36:53 +08:00
Omar Chebib
8ca191e4c1 fix(esp32p4): Fixed interrupt handling to use the CLIC controller 2023-08-31 12:16:08 +08:00
Omar Chebib
5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer
G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
Marius Vikhammer
9362434c47 build-system: add property for architecture (riscv/xtensa)
riscv/xtensa is now a common component.
2022-05-20 09:00:32 +08:00
laokaiyao
cf049e15ed esp8684: rename target to esp32c2 2022-01-19 11:08:57 +08:00
Cao Sen Miao
36f6d16b8d ESP8684: add soc, riscv, newlib support 2021-11-06 17:33:44 +08:00
Shu Chen
75bd02bd46 esp32h2: add some more fixes and TODOs 2021-07-01 20:36:39 +08:00
Shu Chen
ee23a489b9 esp32h2: code clean up 2021-07-01 19:53:50 +08:00
Shu Chen
2b9e8fed71 esp32h2: add esp32h2 build target
Add esp32h2 support in the following components:
 * Kconfig
 * components/esptool_py
 * components/riscv
 * components/xtensa
 * tools
2021-07-01 19:51:33 +08:00
Renz Bagaporo
d920aa52be xtensa: simplify build script 2021-02-26 19:45:48 +08:00
Renz Bagaporo
b1027005df arch: move stdatomic 2021-02-26 18:40:00 +08:00
Renz Bagaporo
91a5770fd2 arch: move shared stack implementation to esp_system 2021-02-26 13:34:29 +08:00
morris
7a71cedf87 interrupt: filter out reserved int number by decoding risc-v JAL instruction 2021-01-05 15:39:46 +08:00
Felipe Neves
ec5acf91ee esp_shared_stack: enable shared stack function for riscv and reenable the unit test 2021-01-05 15:39:46 +08:00
Angus Gratton
fccab8f4ef riscv: Add new arch-level component
Changes come from internal branch commit a6723fc
2020-11-12 09:33:18 +11:00