Validate BitScrambler program headers against the supported format and
hardware limits before using header-derived instruction and LUT sizes.
Also add regression coverage for malformed headers and document that the
program blob must come from a trusted assembler output.
Reject LUT loads that exceed the hardware address space and assemble
each 32-bit LUT word via memcpy so unaligned and partial inputs do not
read past the caller buffer. Add regression tests for oversized and
partial unaligned LUT loads.
Clear the returned handle on loopback creation failure and route
initialized objects through bitscrambler_free so channel ownership and
extra cleanup state cannot leak after partial setup errors. Add a
regression test for the failed create path.
Both newlib and picolibc headers in toolchain 16.1 declare timespec_get()
but the archives do not define it. Provide the missing C11 implementation
through esp_libc, mapping TIME_UTC to clock_gettime(CLOCK_REALTIME).
Closes https://github.com/espressif/esp-idf/issues/18889
Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21, esp32p4, and esp32s31. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
Move 7 trace-related examples (app_trace_basic, app_trace_to_plot,
esp_trace_custom_library, function_tracing, gcov, sysview_tracing,
sysview_tracing_heap_log) from examples/system/ into a dedicated
examples/system/tracing/ subdirectory for better organization.
Update all path references across documentation (en + zh_CN),
build-test-rules, CI configs, Kconfig, and component READMEs.
Configure the shared LCDCAM core clock through guarded LCD and CAM LL APIs,
and unify LCD functional clock LL calls around group IDs across supported targets.
Co-authored-by: Cursor <cursoragent@cursor.com>
- Add bt_osal: event queues, mutexes, semaphores, callouts, etc.
- Add the shared BLE profile task and event queue
- Bring both up and tear them down in the host init/deinit paths
- Add unit tests for the OSAL and the profile task
regi2c (the analog i2c master) is not implemented on FPGA: the
REGI2C_RTC_BUSY poll in the regi2c helpers never completes, so the
2nd-stage bootloader hangs until the WDT resets the chip (observed on
the ESP32-S31 FPGA, bitstream v5.0.0-most-ip).
Stub out the regi2c_impl_* macros in hal/regi2c_impl.h when
HAL_CONFIG(ENV_FPGA) is set, so every regi2c call site is skipped on
FPGA for all current and future targets.
- don't do swapping if result is thrown away
- use correct return code if csd_ver is unknown
- use correct release function
When `heap_caps_malloc`/`heap_caps_calloc` are used for allocation,
`heap_caps_free` should be used to release allocated block.
Rename uhci_ll_rx_set_eof_mode → uhci_ll_rx_enable_eof_modes and its
parameter eof_mode → eof_modes to reflect that multiple EOF modes can
be enabled simultaneously via bitmask. Add bool en parameter so callers
can enable or disable without an outer if-check.
The LCD delay registers configure a delay mode (0=no delay, 1=delay on
rising edge, 2=delay on falling edge), not a tick count. Rename the LL
layer functions and parameters to reflect this, and add
lcd_ll_set_data_delay_mode for esp32s31 and esp32p4.
