Reset the LP SPI peripheral and GPIOs before and after every SPI case so
each test starts from a known-clean baseline, and gate the master on an
explicit slave-armed handshake so the master cannot clock the bus while
the slave is still in its arm prologue. Verify received data against the
expected pattern with bounded waits instead of merely logging it.
Add a dedicated LP SPI multi-device pytest for esp32p4 that runs the
retagged lp_core_spi cases, and tag the LP I2C case accordingly.
The LP SPI driver read and wrote the W0..W15 data buffer registers a
whole 32-bit word at a time, which overran the caller's buffer for
transfers whose length was not a multiple of four bytes and corrupted
the received data. Read and write the data buffer byte-granularly so
sub-word transfers no longer alias adjacent bytes.
The master transfer also programmed the shared bit-length register from
tx_length alone, truncating receive-longer-than-transmit transactions,
and always enabled MOSI even on read-only transfers, clocking out stale
buffer contents. Size each hardware transaction by max(tx_length,
rx_length) and gate MOSI/MISO on the corresponding buffer.
The slave path reused the master's single-shot flow, so it re-triggered
reg_update after preload (clocking out the previous transaction's data)
and offered no way for the caller to publish readiness before the master
started the clock. Split the slave transfer into an arm step that
preloads the buffer and starts the user phase, and a wait step that
blocks on TRANS_DONE and drains only the bytes the master actually
clocked in, tracked in software since reg_usr is not a reliable busy
indicator in slave mode.
Set the LP IO direction for the SPI pads, add
lp_core_lp_spi_bus_deinit() to release the LP GPIO pins, and reset the
LP SPI peripheral at bus initialization so a stale configuration from a
previous run cannot leak into the next.
lp_core_uart_set_pin() unconditionally configured the RTS and CTS GPIO
pins even when flow control was disabled. Only configure the RTS pin
when UART_HW_FLOWCTRL_RTS is set, and the CTS pin when
UART_HW_FLOWCTRL_CTS is set.
Made-with: Cursor
On chips with SOC_LP_GPIO_MATRIX_SUPPORTED (esp32p4, esp32s31), when the
default IOMUX pin is used for LP UART, calling rtc_gpio_iomux_func_sel()
alone only selects the IOMUX function on the pad side but does not set
sig_in_sel=0 on the peripheral side. This leaves the LP UART RX input
still reading from the LP GPIO Matrix (where no signal is connected),
causing RX to receive nothing.
Apply the same fix that was already in the HP UART driver: use
rtc_gpio_iomux_input() / rtc_gpio_iomux_output() which additionally
configure the peripheral to bypass the LP GPIO Matrix for IOMUX pins.
The test was passing without real I2C communication due to a GPIO
mismatch (slave on GPIO 6/7 vs RTC I2C master on GPIO 2/3), single-byte
zero-coincidence, unchecked ULP return values, and an insufficient
RTC I2C timeout.
Fix slave GPIOs, increase test length, check I2C return values, add
proper assertions, and set an adequate RTC I2C timeout.
Co-authored-by: Cursor <cursoragent@cursor.com>
Previously we would calculate the wakeup ticks upon every wakeup using the lp-timer clock frequency,
but this caused the binary to pull in software division functions, increasing the binary size.
This value is now precalculated by the hp-core when we configure the ULP. This saves about 1k bytes.
According to the ESP32-S2/S3 TRM, the output pin's mode is set in the RTC_GPIO_PINn_REG
by programming the RTC_GPIO_PINn_PAD_DRIVER bit. The current ULP RISC-V RTCIO driver
however, incorrectly programs the RTC_IO_TOUCH_PADn_REG register field RTC_IO_TOUCH_PADn_DRV.
This commit fixes the bug.
LP core was unable to boot when system was in deepsleep.
This was due to lp uart init in LP rom using XTAL as clk source,
which is normally powered down during sleep.
This would cause lp uart to get stuck while printing ROM output,
and the app would never boot.
Also fixed wrong wakeup cause used by HP core for ULP wake up
