Current implementation of interrupt wait cycle calculation depends on a
delay and local counter method, which is inaccurate in achieving precise
timeouts. This commit updates the implementaion to use CPU cycles
instead, as they are more accurate.
Closes https://github.com/espressif/esp-idf/pull/18208
Fixes for LP ADC to work when used from the LP core
Closes PM-646, IDFCI-5374, IDFCI-5375, IDFCI-5376, and IDFCI-5377
See merge request espressif/esp-idf!45165
- Removed conditional definitions for various RCC_ATOMIC macros across
multiple files, replacing them with a unified PERIPH_RCC_ATOMIC() macro.
- Updated instances where specific RCC_ATOMIC macros were used to ensure
consistent usage of PERIPH_RCC_ATOMIC().
- Deleted unused uart_share_hw_ctrl.h file as its functionality is now
integrated into the new structure.
This commit sets the calibration parameters for a a given LP ADC unit
and channel to improve the raw LP ADC reading when read from the LP
core. The calibration params are set from the HP core.
This commit fixes the following issues with the LP mailbox when LP core
interrupts are enabled -
1. Removed static storage classifier on the interrupt handler to remove
internal linkage and allow the linker to override the weak symbol.
2. Fixed a bug in the interrupt handler where the ACK bit interrupt was
not being cleared correctly.
3. Fixed a bug in the LP core interrupt handler where the message mask
was not being set correctly.
Closes https://github.com/espressif/esp-idf/issues/18095
The existing spinlock mechanism possibly has an overlap of memory
operations during multi core execution, as visible in CI testing. When
running the example inter_cpu_critical_section, shared count increment
stops at 299999 instead of reaching 300000, but this only happens
randomly 1 out of 10 times. It is suspected that a memory operation
happens simultaneously from both core, even though spinlock protection
is in place.
To handle this problem, a memory barrier (fence instruction) is added
at critical places during spinlock acquire and release, to ensure that
all memory operations upto that point are completed and synchronised
before proceeding further.
lp_core_i2c.h header file has sda and scl pins hardcoded to GPIO6 and
GPIO7 which works only for ESP32C6. ESP32C5 uses GPIO2 and GPIO3 for
I2C SDA and SCL. Hence, added LP_I2C_SCL_IO and LP_I2C_SDA_IO macros
under conditional compilation in library header file, so there is no
need to hardcode I2C GPIO pins and any other test apps or examples
that are including the LP I2C header file can also use Macro directly.
This commit updates the lp_core_uart_tx_flush() API to wait for the Tx line
to become idle, therefore confirming that all bytes are sent out.
Closes https://github.com/espressif/esp-idf/issues/15433
