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42,511 Commits 25 Branches 192 Tags
0b01a18fc9544bbaeacd1206873aca7cdb576b30
Commit Graph
45 Commits
Author SHA1 Message Date
harshal.patil b0442de937 fix(bootloader_support): Allow pre-programmed XTS-AES psuedo round level efuses 
- The API esp_flash_encryption_set_release_mode() by defualt programs
the XTS-AES pseudo round level efuse to level low but did not considered
any existing value that would have been programmed in the efuse bit.
 2025-09-30 15:19:26 +05:30
harshal.patil c3c15d240e fix(bootloader_support): Reorder write protection bits of some shared security efuses 2025-09-30 14:57:12 +05:30
nilesh.kale 19fcf0e073 feat: enabled ECDSA-P192 support for ESP32H2 2025-06-24 15:03:59 +05:30
harshal.patil ac0dc0d775 feat(bootloader_support): Permanently enable XTS-AES pseudo rounds when FE release mode is enabled 2025-01-23 14:06:16 +05:30
laokaiyao 2abf73d94c refactor(lpperi): improve compatibility solution 2025-01-16 10:18:02 +08:00
laokaiyao 90457a9a4e refactor(lpperi): compatible refactor for H2 ECO5 2025-01-13 14:39:33 +08:00
zlq 0e37fdd1b0 fix: fix pll low temp bug (v5.3) 2024-11-27 19:17:48 +08:00
wuzhenghui 0b920ec08a change(esp_phy): close esp32h2 rf pll by default 2024-03-12 10:10:41 +08:00
KonstantinKondrashov b471d9d22c change(all): Clearing unused efuse rom headers 2024-01-22 18:02:55 +02:00
Xiao Xufeng 28f19cf0e6 fix(ram_app): Fixed issue ram_app can't use the SPI Flash 
1st bootloader won't help to initialize the MSPI & cache properly as it
usually do when loading from flash. And the ram app doesn't have valid
headers.

Since there is no enough space in 2nd bootloader, we replace the
`bootloader_init_spi_flash` in the ram_app (!pure_ram_app), with an
customized alternative of it for the ram_app.

This alternative helps to initialize the MSPI & cache properly, without
the help of 1st bootloader or image headers.
 2023-11-01 02:01:45 +08:00
Marius Vikhammer e3861261eb fix(wdt): move non-auto generated wdt values to ll 2023-09-05 11:52:34 +08:00
Lou Tianhao 7fd74057a3 example: bringup light sleep example for esp32h2 2023-06-26 21:05:16 +08:00
Michael (XIAO Xufeng) c7b852b7c7 bootloader: fix analog reset on C6 and H2 2023-04-11 10:23:20 +08:00
Mahavir Jain f22daec784 Merge branch 'feature/secure_set_efuses_to_prevent_brick_chip' into 'master' 
security: write-protect DIS_ICAHE and DIS_DCACHE

Closes IDF-5177

See merge request espressif/esp-idf!22640
 2023-03-29 11:51:09 +08:00
KonstantinKondrashov a3232e4a5b bootloader: Adds an option to leave DIS_CACHE writeable 2023-03-29 00:02:25 +08:00
KonstantinKondrashov 723b2e86e5 security: write-protect DIS_ICAHE and DIS_DCACHE 
Closes IDF-5177
 2023-03-29 00:02:24 +08:00
Armando bae6680207 mmu: hal function to init, and hal function to unmap all 2023-03-15 10:59:20 +08:00
Armando 929b7717ff system: fixed ram app cannot use mmu correctly issue 2023-03-15 10:59:20 +08:00
Mahavir Jain d4ccdd48f6 esp32h2: add secure boot feature support 
Closes IDF-6281
 2023-03-06 16:57:45 +05:30
Armando 89fa53f1c0 mmu: support configurable mmu page size 2023-03-04 02:48:40 +00:00
KonstantinKondrashov f3394c488a efuse: Add support for esp32h2 2023-02-21 08:18:14 +00:00
Song Ruo Jing 2c2a62e323 clk_tree: Add basic clock support for esp32h2 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration

Remove FPGA build for esp32h2
 2023-02-20 17:15:02 +08:00
wuzhenghui 146b9b047b soc: add modem regs and force enable i2c_ana_mst clock 2023-02-06 21:43:26 +08:00
wuzhenghui c0d2fcded7 refactor: move bootloader_init_spi_flash to bootloader_flash_config_{target}.c 2023-02-01 17:57:28 +08:00
wuzhenghui 44df5b31af feature: add ram loadable app support 2023-02-01 17:57:22 +08:00
Cao Sen Miao 4713a9a7f2 ESP32H2: Introduce new chip target esp32h2, hello_world example supported 2022-12-29 12:29:14 +08:00
laokaiyao 8677216576 esp32h2: renaming esp32h2 to esp32h4 2022-11-08 17:05:33 +08:00
Jakob Hasse 33a3616635 refactor (bootloader_support, efuse)!: remove target-specific rom includes 
The following two functions in bootloader_support are private now:
* esp_secure_boot_verify_sbv2_signature_block()
* esp_secure_boot_verify_rsa_signature_block()
They have been moved into private header files
inside bootloader_private/

* Removed bootloader_reset_reason.h and
  bootloader_common_get_reset_reason() completely.
  Alternative in ROM component is available.

* made esp_efuse.h independent of target-specific rom header
 2022-07-13 10:29:02 +08:00
Wu Zheng Hui b98622c624 efuse: update efuse name 2022-05-28 22:03:16 +08:00
Cao Sen Miao 4418a855ba spi_flash: refactor the spi_flash clock configuration, and add support for esp32c2 2022-04-26 15:22:37 +08:00
Michael (XIAO Xufeng) aab535fe4a Merge branch 'bugfix/regi2c_ctrl_spinlock_s2' into 'master' 
hw_support: fixed regi2c not protected by lock on ESP32S2

See merge request espressif/esp-idf!16653
 2022-03-13 02:47:53 +08:00
Michael (XIAO Xufeng) d5bdf95580 hw_support: fixed regi2c not protected by lock on ESP32S2 2022-03-13 00:24:08 +08:00
Armando c1cbd7bbf6 cache/mmu: implememnt cache and mmu hal APIs in bootloader 2022-03-11 22:43:11 +08:00
KonstantinKondrashov f761cee32e bootloader_support: Removes old code of SB and FE for esp32h2 2022-01-26 15:21:20 +08:00
Cao Sen Miao 3dd1cfea18 spi_flash: refactor spi_flash.h to decline duplicated code 2021-12-30 14:05:12 +08:00
Sudeep Mohanty e22b4007d3 esp_hw_support: Removed deprecated CPU util functions 
The following files were deleted:
- components/esp_hw_support/include/soc/cpu.h
- components/soc/esp32s3/include/soc/cpu.h

The following functions are deprecated:
- get_sp()

The following functions declared in soc/cpu.h are now moved to esp_cpu.h:
- esp_cpu_configure_region_protection()

The following functions declared in soc/cpu.h are now moved to components/xtensa/include/esp_cpu_utils.h:
- esp_cpu_process_stack_pc()

All files with soc/cpu.h inclusion are updated to include esp_cpu.h instead.

Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com>
 2021-12-28 16:58:37 +05:30
Aditya Patwardhan 5d61eea847 efuse_example_test: Fix the example test ( broken due to latest change 
in info message)

*Unify the log messages when UART ROM Download mode is kept enabled
 2021-11-23 15:21:32 +05:30
Aditya Patwardhan be65338212 secure_boot: Fix warning when UART ROM DL mode is disabled 
*Additionally use updated calls to enable rom secure download mode
 2021-11-22 12:01:15 +05:30
Sachin Parekh bf1dde7233 bootloader: Enable clock glitch detection 
Reset the device when clock glitch detected. Clock glitch detection is
only active in bootloader
 2021-09-02 12:25:12 +05:30
wuzhenghui 6ab495b4dc esp32h2: chip env support 
brownout init fixed
 2021-08-25 11:02:47 +08:00
Michael (XIAO Xufeng) dd40123129 bootloader: add xmc spi_flash startup flow to improve reliability 2021-08-12 17:22:42 +08:00
Cao Sen Miao c29b3e2e36 spi_flash: move the unlock patch to bootloader and add support for GD 2021-07-29 10:46:33 +08:00
KonstantinKondrashov 92448e7bd7 secure_boot: Whole 3 bits are set for SOFT_DIS_JTAG eFuse 2021-07-21 17:19:01 +05:00
morris 1560d6f1ba soc: add reset reasons in soc component 2021-07-13 10:45:38 +08:00
Shu Chen c0056813f2 esp32h2: add bootloader support 2021-07-01 19:53:11 +08:00