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release/v6.1
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6 Commits
Author SHA1 Message Date
Alexey Lapshin a494009a0c feat(build): add RISC-V ZCMP post-link workaround check 
Validate linked RISC-V executables when
CONFIG_COMPILER_ENABLE_RISCV_ZCMP is enabled on affected chips.
Disassemble each function and reject mstatus.MIE clears that lack an
earlier mintthresh write of 0xff.

Handle csrrci, csrrw, and register-mask csrrc patterns while ignoring
csrrs. Add build-only coverage for valid and invalid sequences with
CMake v1 and v2.

Stop the hardware stack guard before switching stacks during restart,
and keep ZCMP disabled for TEE test apps that still require the
workaround.
 2026-08-03 14:10:00 +08:00
Laukik Hase 4c39f0d006 ci(hal): Extend support for ESP32-P4 for the PMS HAL test-app 2026-05-21 13:42:18 +05:30
Laukik Hase 99f6d7cd56 ci(hal): Enable the TEE-based interrupt test-cases for ESP32-P4 2026-02-18 11:46:15 +05:30
Aditya Patwardhan 4ca334d3a7 fix(docs): Fix docs after esp_hal_security update 2026-01-21 10:02:47 +05:30
Aditya Patwardhan eb4a871eca refactor(esp_hal_security): Updated esp_hal_security build and includes 2026-01-21 10:02:44 +05:30
Aditya Patwardhan 5ee7af3afd refactor(hal): Created esp_hal_security for security code 2026-01-21 09:59:46 +05:30