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release/v6.1
Commit Graph
22 Commits
Author SHA1 Message Date
muhaidong f5cf14b319 fix(wifi): fix regdma restore ba bitmap fail issue 2026-09-15 20:51:25 +08:00
morrisandCursor ef6b7b742f refactor(lcdcam): move shared core clock setup to drivers 
Configure the shared LCDCAM core clock through guarded LCD and CAM LL APIs,
and unify LCD functional clock LL calls around group IDs across supported targets.

Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-08 14:47:41 +08:00
wuzhenghui 4ffb72cbc1 fix(esp_hw_support): fix ESP32-S31 CPU/DFS clk_tree refcount and keep clock source during DFS 2026-09-03 19:36:37 +08:00
wuzhenghui f9428ecc1e feat(esp_hw_support): support esp32s31 clock tree management 2026-09-02 19:20:13 +08:00
Armando (Dou Yiwen) 36fc263512 fix(mpll): improved mpll calibration flow on esp32s31 
Signed-off-by: Armando (Dou Yiwen) <douyiwen@espressif.com>
 2026-08-25 10:50:09 +08:00
wuzhenghui 7c23080017 fix(esp_hw_support): fix esp32s31 mpll initialization 2026-07-06 21:17:34 +08:00
wuzhenghui ce0fcbaa9a feat(esp_system): support esp32s31 esp_perip_clk_init 2026-06-15 10:31:06 +08:00
Ondrej Kosta c7d6c41198 feat(clk_tree): support derived PLL clocks 
Add a generic derived-PLL clock engine to esp_clk_tree_common that
handles acquire/release, mux selection, and divider programming for
target-defined derived clocks. Per-target descriptors (ESP32-P4,
ESP32-S31) plug into the engine via
esp_clk_tree_get_derived_clk_desc().
 2026-05-21 15:59:42 +08:00
armando f408e1a8bc feat(sdmmc): add esp32s31 support 
Enable SDMMC host support on ESP32-S31 across HAL, SOC caps, tests, examples, and documentation.
 2026-05-21 09:09:28 +08:00
gaoxu 4e3751b32e feat(cam): support dvp cam on ESP32-S31 2026-05-14 17:09:49 +08:00
wuzhenghui 3f6957450f feat(esp_hw_support): support psram PD_TOP retention 2026-05-07 12:02:01 +08:00
wuzhenghui f1f3f204fe feat(esp_hw_support): support esp32s31 lightsleep/deepsleep example 2026-05-06 20:15:01 +08:00
hongshuqing 7c665c106c fix(pmu): update cpll_bbpll_apll_mpll enable config 2026-04-27 14:30:19 +08:00
laokaiyao 8d0fca08a0 feat(i2s): support i2s & apll on esp32s31 2026-04-22 09:30:53 +08:00
Chen Ji Chang 83e7b11716 Merge branch 'feat/lcd_use_apll_clock' into 'master' 
refactor(clk_tree): use general api to enable the clk

Closes IDF-11478 and IDF-12972

See merge request espressif/esp-idf!35952
 2026-04-20 22:12:01 +08:00
Xorlent 51d059232b Fix output bit range in bitscrambler documentation 
Destination bit range incorrect in `Sub-instructions` example
 2026-04-17 17:20:28 +08:00
Chen Jichang 6e206dd173 refactor(clk_tree): use general api to enable the clk 2026-04-16 20:03:06 +08:00
wuzhenghui b913f147ba feat(esp_hw_support): support esp32s31 esp_clock_output 2026-04-14 12:19:07 +08:00
Song Ruo Jing 50051b74a5 feat(clk): support for esp32s31 clock tree 2026-04-02 20:39:59 +08:00
armando ebbd9cdb59 feat(psram): support psram device driver 2026-03-31 13:56:43 +08:00
Song Ruo Jing 600bf5b6d7 refactor(esp_hal_regi2c): move regi2c implementation from esp_rom to esp_hal_regi2c 2026-03-10 15:08:51 +08:00
Song Ruo Jing 62511d61e9 refactor(clk): split clock HAL into separate component 2026-01-13 15:50:20 +08:00